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Generic CPUs / accelerators patch queue

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- Merge "qemu/clang-tsa.h" within "qemu/compiler.h"
 - Various cleanups around accelerators initialization code
   (better user/system split)
 - Various trivial cleanups in accel/tcg/,
   Guard few TCG calls with tcg_enabled()
 - Explicit disassemble_info endianness
 - Improve dual-endianness support for MicroBlaze
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Merge tag 'accel-cpus-20250306' of https://github.com/philmd/qemu into staging

Generic CPUs / accelerators patch queue

- Merge "qemu/clang-tsa.h" within "qemu/compiler.h"
- Various cleanups around accelerators initialization code
  (better user/system split)
- Various trivial cleanups in accel/tcg/,
  Guard few TCG calls with tcg_enabled()
- Explicit disassemble_info endianness
- Improve dual-endianness support for MicroBlaze

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* tag 'accel-cpus-20250306' of https://github.com/philmd/qemu: (54 commits)
  include: Poison TARGET_PHYS_ADDR_SPACE_BITS definition
  system: Open-code qemu_init_arch_modules() using target_name()
  target/i386: Mark WHPX APIC region as little-endian
  target/alpha: Do not mix exception flags and FPCR bits
  target/riscv: Convert misa_mxl_max using GLib macros
  target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL
  target/xtensa: Finalize config in xtensa_register_core()
  target/sparc: Constify SPARCCPUClass::cpu_def
  target/i386: Constify X86CPUModel uses
  disas: Remove target_words_bigendian() call in initialize_debug_target()
  target/xtensa: Set disassemble_info::endian value in disas_set_info()
  target/sh4: Set disassemble_info::endian value in disas_set_info()
  target/riscv: Set disassemble_info::endian value in disas_set_info()
  target/ppc: Set disassemble_info::endian value in disas_set_info()
  target/mips: Set disassemble_info::endian value in disas_set_info()
  target/microblaze: Set disassemble_info::endian value in disas_set_info
  target/arm: Set disassemble_info::endian value in disas_set_info()
  target: Set disassemble_info::endian value for big-endian targets
  target: Set disassemble_info::endian value for little-endian targets
  target/mips: Fix possible MSA int overflow
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2025-03-07 07:39:49 +08:00
commit 98c7362b1e
110 changed files with 544 additions and 533 deletions
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3
target/sparc/cpu.c
View file

@ -106,6 +106,7 @@ static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info)
{
info->print_insn = print_insn_sparc;
info->endian = BFD_ENDIAN_BIG;
#ifdef TARGET_SPARC64
info->mach = bfd_mach_sparc_v9b;
#endif
@ -993,7 +994,7 @@ static const struct SysemuCPUOps sparc_sysemu_ops = {
#endif
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps sparc_tcg_ops = {
.initialize = sparc_tcg_init,