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Sixth RISC-V PR for 8.0

Browse source 
* Support for the Zicbiom, ZCicboz, and Zicbop extensions.
 * OpenSBI has been updated to version 1.2, see
   <https://github.com/riscv-software-src/opensbi/releases/tag/v1.2> for
   the release notes.
 * Support for setting the virtual address width (ie, sv39/sv48/sv57) on
   the command line.
 * Support for ACPI on RISC-V.
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Merge tag 'pull-riscv-to-apply-20230306' of https://gitlab.com/palmer-dabbelt/qemu into staging

Sixth RISC-V PR for 8.0

* Support for the Zicbiom, ZCicboz, and Zicbop extensions.
* OpenSBI has been updated to version 1.2, see
  <https://github.com/riscv-software-src/opensbi/releases/tag/v1.2> for
  the release notes.
* Support for setting the virtual address width (ie, sv39/sv48/sv57) on
  the command line.
* Support for ACPI on RISC-V.

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# gpg: Signature made Mon 06 Mar 2023 21:51:36 GMT
# gpg:                using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889
# gpg:                issuer "palmer@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown]
# gpg:                 aka "Palmer Dabbelt <palmerdabbelt@google.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41
#      Subkey fingerprint: 2B3C 3747 4468 43B2 4A94  3A7A 2E13 19F3 5FBB 1889

* tag 'pull-riscv-to-apply-20230306' of https://gitlab.com/palmer-dabbelt/qemu: (22 commits)
  MAINTAINERS: Add entry for RISC-V ACPI
  hw/riscv/virt.c: Initialize the ACPI tables
  hw/riscv/virt: virt-acpi-build.c: Add RHCT Table
  hw/riscv/virt: virt-acpi-build.c: Add RINTC in MADT
  hw/riscv/virt: Enable basic ACPI infrastructure
  hw/riscv/virt: Add memmap pointer to RiscVVirtState
  hw/riscv/virt: Add a switch to disable ACPI
  hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fields
  riscv: Correctly set the device-tree entry 'mmu-type'
  riscv: Introduce satp mode hw capabilities
  riscv: Allow user to set the satp mode
  riscv: Change type of valid_vm_1_10_[32|64] to bool
  riscv: Pass Object to register_cpu_props instead of DeviceState
  roms/opensbi: Upgrade from v1.1 to v1.2
  gitlab/opensbi: Move to docker:stable
  hw: intc: Use cpu_by_arch_id to fetch CPU state
  target/riscv: cpu: Implement get_arch_id callback
  disas/riscv Fix ctzw disassemble
  hw/riscv/virt.c: add cbo[mz]-block-size fdt properties
  target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2023-03-07 12:53:00 +00:00
commit 9832009d9d
23 changed files with 1061 additions and 61 deletions
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57
target/riscv/insn_trans/trans_rvzicbo.c.inc Normal file
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/*
* RISC-V translation routines for the RISC-V CBO Extension.
*
* Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#define REQUIRE_ZICBOM(ctx) do { \
if (!ctx->cfg_ptr->ext_icbom) { \
return false; \
} \
} while (0)
#define REQUIRE_ZICBOZ(ctx) do { \
if (!ctx->cfg_ptr->ext_icboz) { \
return false; \
} \
} while (0)
static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
{
REQUIRE_ZICBOM(ctx);
gen_helper_cbo_clean_flush(cpu_env, cpu_gpr[a->rs1]);
return true;
}
static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
{
REQUIRE_ZICBOM(ctx);
gen_helper_cbo_clean_flush(cpu_env, cpu_gpr[a->rs1]);
return true;
}
static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
{
REQUIRE_ZICBOM(ctx);
gen_helper_cbo_inval(cpu_env, cpu_gpr[a->rs1]);
return true;
}
static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
{
REQUIRE_ZICBOZ(ctx);
gen_helper_cbo_zero(cpu_env, cpu_gpr[a->rs1]);
return true;
}