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target/openrisc: Keep SR_CY and SR_OV in a separate variables
This significantly streamlines carry and overflow production. Signed-off-by: Richard Henderson <rth@twiddle.net>
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parent
84775c43f3
commit
9745807191
4 changed files with 78 additions and 89 deletions
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@ -30,13 +30,32 @@ void HELPER(exception)(CPUOpenRISCState *env, uint32_t excp)
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raise_exception(cpu, excp);
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}
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void HELPER(ove)(CPUOpenRISCState *env, target_ulong test)
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static void QEMU_NORETURN do_range(CPUOpenRISCState *env, uintptr_t pc)
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{
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if (unlikely(test)) {
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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cs->exception_index = EXCP_RANGE;
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cpu_loop_exit_restore(cs, GETPC());
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cs->exception_index = EXCP_RANGE;
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cpu_loop_exit_restore(cs, pc);
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}
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void HELPER(ove_cy)(CPUOpenRISCState *env)
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{
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if (env->sr_cy) {
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do_range(env, GETPC());
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}
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}
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void HELPER(ove_ov)(CPUOpenRISCState *env)
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{
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if (env->sr_ov < 0) {
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do_range(env, GETPC());
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}
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}
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void HELPER(ove_cyov)(CPUOpenRISCState *env)
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{
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if (env->sr_cy || env->sr_ov < 0) {
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do_range(env, GETPC());
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}
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}
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