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hw/misc/aspeed_hace: Rename R_HASH_DEST to R_HASH_DIGEST and introduce 64-bit hash digest address helper

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Renaming R_HASH_DEST to R_HASH_DIGEST for better semantic clarity.

The AST2700 CPU, based on the Cortex-A35, features a 64-bit DRAM address space.
To prepare for future AST2700 support, this change introduces a new helper
function hash_get_digest_addr() to encapsulate digest address extraction logic
and improve code readability.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250515081008.583578-11-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-05-15 16:09:42 +08:00 • committed by Cédric Le Goater
parent c6c5fc5ab0
commit 973fab3b30
1 changed files with 19 additions and 6 deletions
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25
hw/misc/aspeed_hace.c
View file

@ -27,7 +27,7 @@
#define TAG_IRQ BIT(15)
#define R_HASH_SRC (0x20 / 4)
#define R_HASH_DEST (0x24 / 4)
#define R_HASH_DIGEST (0x24 / 4)
#define R_HASH_KEY_BUFF (0x28 / 4)
#define R_HASH_SRC_LEN (0x2c / 4)
@ -238,17 +238,30 @@ static int hash_prepare_sg_iov(AspeedHACEState *s, struct iovec *iov,
return iov_idx;
}
static uint64_t hash_get_digest_addr(AspeedHACEState *s)
{
uint64_t digest_addr = 0;
digest_addr = deposit64(digest_addr, 0, 32, s->regs[R_HASH_DIGEST]);
return digest_addr;
}
static void hash_write_digest_and_unmap_iov(AspeedHACEState *s,
struct iovec *iov,
int iov_idx,
uint8_t *digest_buf,
size_t digest_len)
{
if (address_space_write(&s->dram_as, s->regs[R_HASH_DEST],
MEMTXATTRS_UNSPECIFIED, digest_buf, digest_len)) {
uint64_t digest_addr = 0;
digest_addr = hash_get_digest_addr(s);
if (address_space_write(&s->dram_as, digest_addr,
MEMTXATTRS_UNSPECIFIED,
digest_buf, digest_len)) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Failed to write digest to 0x%x\n",
__func__, s->regs[R_HASH_DEST]);
"%s: Failed to write digest to 0x%" HWADDR_PRIx "\n",
__func__, digest_addr);
}
for (; iov_idx > 0; iov_idx--) {
@ -402,7 +415,7 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data,
case R_HASH_SRC:
data &= ahc->src_mask;
break;
case R_HASH_DEST:
case R_HASH_DIGEST:
data &= ahc->dest_mask;
break;
case R_HASH_KEY_BUFF: