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virtio, pci, pc: fixes, features
Bugfixes all over the place. HMAT support. New flags for vhost-user-blk utility. Auto-tuning of seg max for virtio storage. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> -----BEGIN PGP SIGNATURE----- iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAl4TaMEPHG1zdEByZWRo YXQuY29tAAoJECgfDbjSjVRpvzgH/2LyDAzCa9h93ikSJjmyUk5FUaqve38daEb3 S3JYjwKxQx7u1ydooKhvBQnBCZ2i3S+k62gfYyKB+nBv8xvjs0Eg5D1YJ5E8hciy lf5OFGWWtX2iPDjZwQwT13kiJe0o3JRGxJJ6XqTEG+1EYOp7cky/FEv4PD030b9m I2wROZ/Am+onB9YJX8c0Vv1CG+AryuJNXnvwQzTXEjj4U7bEYUyJwVZaCRyAdWQ3 uYXIZN9VwjVX6BFvy9ZAJbEsUVJvOM1/aQaDqcrLz+VlzRT7bRkKHi2G3vakrm1I r5OpgyLo84132awCncbSykKDH5o8WaxLaJBjGmuBfasMz9wPzAg= =uL1o -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging virtio, pci, pc: fixes, features Bugfixes all over the place. HMAT support. New flags for vhost-user-blk utility. Auto-tuning of seg max for virtio storage. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Mon 06 Jan 2020 17:05:05 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (32 commits) intel_iommu: add present bit check for pasid table entries intel_iommu: a fix to vtd_find_as_from_bus_num() virtio-net: delete also control queue when TX/RX deleted virtio: reset region cache when on queue deletion virtio-mmio: update queue size on guest write tests: add virtio-scsi and virtio-blk seg_max_adjust test virtio: make seg_max virtqueue size dependent hw: fix using 4.2 compat in 5.0 machine types for i440fx/q35 vhost-user-scsi: reset the device if supported vhost-user: add VHOST_USER_RESET_DEVICE to reset devices hw/pci/pci_host: Let pci_data_[read/write] use unsigned 'size' argument hw/pci/pci_host: Remove redundant PCI_DPRINTF() virtio-mmio: Clear v2 transport state on soft reset ACPI: add expected files for HMAT tests (acpihmat) tests/bios-tables-test: add test cases for ACPI HMAT tests/numa: Add case for QMP build HMAT hmat acpi: Build Memory Side Cache Information Structure(s) hmat acpi: Build System Locality Latency and Bandwidth Information Structure(s) hmat acpi: Build Memory Proximity Domain Attributes Structure(s) numa: Extend CLI to provide memory side cache information ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
973d306dd6
45 changed files with 1796 additions and 133 deletions
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@ -426,10 +426,14 @@
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#
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# @cpu: property based CPU(s) to node mapping (Since: 2.10)
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#
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# @hmat-lb: memory latency and bandwidth information (Since: 5.0)
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#
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# @hmat-cache: memory side cache information (Since: 5.0)
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#
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# Since: 2.1
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##
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{ 'enum': 'NumaOptionsType',
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'data': [ 'node', 'dist', 'cpu' ] }
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'data': [ 'node', 'dist', 'cpu', 'hmat-lb', 'hmat-cache' ] }
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##
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# @NumaOptions:
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@ -444,7 +448,9 @@
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'data': {
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'node': 'NumaNodeOptions',
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'dist': 'NumaDistOptions',
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'cpu': 'NumaCpuOptions' }}
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'cpu': 'NumaCpuOptions',
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'hmat-lb': 'NumaHmatLBOptions',
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'hmat-cache': 'NumaHmatCacheOptions' }}
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##
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# @NumaNodeOptions:
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@ -463,6 +469,13 @@
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# @memdev: memory backend object. If specified for one node,
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# it must be specified for all nodes.
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#
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# @initiator: defined in ACPI 6.3 Chapter 5.2.27.3 Table 5-145,
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# points to the nodeid which has the memory controller
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# responsible for this NUMA node. This field provides
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# additional information as to the initiator node that
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# is closest (as in directly attached) to this node, and
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# therefore has the best performance (since 5.0)
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#
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# Since: 2.1
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##
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{ 'struct': 'NumaNodeOptions',
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@ -470,7 +483,8 @@
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'*nodeid': 'uint16',
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'*cpus': ['uint16'],
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'*mem': 'size',
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'*memdev': 'str' }}
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'*memdev': 'str',
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'*initiator': 'uint16' }}
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##
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# @NumaDistOptions:
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@ -549,6 +563,166 @@
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'base': 'CpuInstanceProperties',
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'data' : {} }
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##
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# @HmatLBMemoryHierarchy:
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#
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# The memory hierarchy in the System Locality Latency and Bandwidth
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# Information Structure of HMAT (Heterogeneous Memory Attribute Table)
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#
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# For more information about @HmatLBMemoryHierarchy, see chapter
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# 5.2.27.4: Table 5-146: Field "Flags" of ACPI 6.3 spec.
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#
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# @memory: the structure represents the memory performance
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#
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# @first-level: first level of memory side cache
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#
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# @second-level: second level of memory side cache
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#
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# @third-level: third level of memory side cache
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#
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# Since: 5.0
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##
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{ 'enum': 'HmatLBMemoryHierarchy',
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'data': [ 'memory', 'first-level', 'second-level', 'third-level' ] }
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##
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# @HmatLBDataType:
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#
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# Data type in the System Locality Latency and Bandwidth
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# Information Structure of HMAT (Heterogeneous Memory Attribute Table)
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#
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# For more information about @HmatLBDataType, see chapter
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# 5.2.27.4: Table 5-146: Field "Data Type" of ACPI 6.3 spec.
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#
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# @access-latency: access latency (nanoseconds)
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#
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# @read-latency: read latency (nanoseconds)
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#
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# @write-latency: write latency (nanoseconds)
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#
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# @access-bandwidth: access bandwidth (Bytes per second)
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#
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# @read-bandwidth: read bandwidth (Bytes per second)
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#
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# @write-bandwidth: write bandwidth (Bytes per second)
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#
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# Since: 5.0
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##
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{ 'enum': 'HmatLBDataType',
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'data': [ 'access-latency', 'read-latency', 'write-latency',
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'access-bandwidth', 'read-bandwidth', 'write-bandwidth' ] }
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##
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# @NumaHmatLBOptions:
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#
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# Set the system locality latency and bandwidth information
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# between Initiator and Target proximity Domains.
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#
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# For more information about @NumaHmatLBOptions, see chapter
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# 5.2.27.4: Table 5-146 of ACPI 6.3 spec.
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#
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# @initiator: the Initiator Proximity Domain.
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#
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# @target: the Target Proximity Domain.
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#
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# @hierarchy: the Memory Hierarchy. Indicates the performance
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# of memory or side cache.
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#
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# @data-type: presents the type of data, access/read/write
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# latency or hit latency.
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#
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# @latency: the value of latency from @initiator to @target
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# proximity domain, the latency unit is "ns(nanosecond)".
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#
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# @bandwidth: the value of bandwidth between @initiator and @target
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# proximity domain, the bandwidth unit is
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# "Bytes per second".
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#
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# Since: 5.0
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##
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{ 'struct': 'NumaHmatLBOptions',
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'data': {
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'initiator': 'uint16',
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'target': 'uint16',
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'hierarchy': 'HmatLBMemoryHierarchy',
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'data-type': 'HmatLBDataType',
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'*latency': 'uint64',
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'*bandwidth': 'size' }}
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##
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# @HmatCacheAssociativity:
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#
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# Cache associativity in the Memory Side Cache Information Structure
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# of HMAT
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#
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# For more information of @HmatCacheAssociativity, see chapter
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# 5.2.27.5: Table 5-147 of ACPI 6.3 spec.
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#
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# @none: None (no memory side cache in this proximity domain,
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# or cache associativity unknown)
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#
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# @direct: Direct Mapped
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#
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# @complex: Complex Cache Indexing (implementation specific)
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#
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# Since: 5.0
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##
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{ 'enum': 'HmatCacheAssociativity',
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'data': [ 'none', 'direct', 'complex' ] }
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##
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# @HmatCacheWritePolicy:
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#
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# Cache write policy in the Memory Side Cache Information Structure
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# of HMAT
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#
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# For more information of @HmatCacheWritePolicy, see chapter
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# 5.2.27.5: Table 5-147: Field "Cache Attributes" of ACPI 6.3 spec.
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#
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# @none: None (no memory side cache in this proximity domain,
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# or cache write policy unknown)
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#
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# @write-back: Write Back (WB)
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#
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# @write-through: Write Through (WT)
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#
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# Since: 5.0
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##
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{ 'enum': 'HmatCacheWritePolicy',
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'data': [ 'none', 'write-back', 'write-through' ] }
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##
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# @NumaHmatCacheOptions:
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#
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# Set the memory side cache information for a given memory domain.
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#
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# For more information of @NumaHmatCacheOptions, see chapter
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# 5.2.27.5: Table 5-147: Field "Cache Attributes" of ACPI 6.3 spec.
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#
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# @node-id: the memory proximity domain to which the memory belongs.
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#
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# @size: the size of memory side cache in bytes.
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#
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# @level: the cache level described in this structure.
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#
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# @associativity: the cache associativity,
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# none/direct-mapped/complex(complex cache indexing).
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#
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# @policy: the write policy, none/write-back/write-through.
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#
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# @line: the cache Line size in bytes.
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#
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# Since: 5.0
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##
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{ 'struct': 'NumaHmatCacheOptions',
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'data': {
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'node-id': 'uint32',
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'size': 'size',
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'level': 'uint8',
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'associativity': 'HmatCacheAssociativity',
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'policy': 'HmatCacheWritePolicy',
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'line': 'uint16' }}
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##
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# @HostMemPolicy:
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#
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