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target/avr: Add instruction translation - Data Transfer Instructions

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This includes:
    - MOV, MOVW
    - LDI, LDS LDX LDY LDZ
    - LDDY, LDDZ
    - STS, STX STY STZ
    - STDY, STDZ
    - LPM, LPMX
    - ELPM, ELPMX
    - SPM, SPMX
    - IN, OUT
    - PUSH, POP
    - XCH
    - LAS, LAC LAT

Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20200705140315.260514-14-huth@tuxfamily.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Michael Rolnik 2020-01-24 01:51:12 +01:00 • committed by Philippe Mathieu-Daudé
parent 9d316c75ab
commit 9732b024f7
2 changed files with 1046 additions and 0 deletions
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56
target/avr/insn.decode
View file

@ -107,3 +107,59 @@ SBIC 1001 1001 reg:5 bit:3
SBIS 1001 1011 reg:5 bit:3
BRBS 1111 00 ....... ... @op_bit_imm
BRBC 1111 01 ....... ... @op_bit_imm
#
# Data Transfer Instructions
#
%rd_d 4:4 !function=to_regs_00_30_by_two
%rr_d 0:4 !function=to_regs_00_30_by_two
@io_rd_imm .... . .. ..... .... &rd_imm rd=%rd imm=%io_imm
@ldst_d .. . . .. . rd:5 . ... &rd_imm imm=%ldst_d_imm
# The 16-bit immediate is completely in the next word.
# Fields cannot be defined with no bits, so we cannot play
# the same trick and append to a zero-bit value.
# Defer reading the immediate until trans_{LDS,STS}.
@ldst_s .... ... rd:5 .... imm=0
MOV 0010 11 . ..... .... @op_rd_rr
MOVW 0000 0001 .... .... &rd_rr rd=%rd_d rr=%rr_d
LDI 1110 .... .... .... @op_rd_imm8
LDS 1001 000 ..... 0000 @ldst_s
LDX1 1001 000 rd:5 1100
LDX2 1001 000 rd:5 1101
LDX3 1001 000 rd:5 1110
LDY2 1001 000 rd:5 1001
LDY3 1001 000 rd:5 1010
LDZ2 1001 000 rd:5 0001
LDZ3 1001 000 rd:5 0010
LDDY 10 . 0 .. 0 ..... 1 ... @ldst_d
LDDZ 10 . 0 .. 0 ..... 0 ... @ldst_d
STS 1001 001 ..... 0000 @ldst_s
STX1 1001 001 rr:5 1100
STX2 1001 001 rr:5 1101
STX3 1001 001 rr:5 1110
STY2 1001 001 rd:5 1001
STY3 1001 001 rd:5 1010
STZ2 1001 001 rd:5 0001
STZ3 1001 001 rd:5 0010
STDY 10 . 0 .. 1 ..... 1 ... @ldst_d
STDZ 10 . 0 .. 1 ..... 0 ... @ldst_d
LPM1 1001 0101 1100 1000
LPM2 1001 000 rd:5 0100
LPMX 1001 000 rd:5 0101
ELPM1 1001 0101 1101 1000
ELPM2 1001 000 rd:5 0110
ELPMX 1001 000 rd:5 0111
SPM 1001 0101 1110 1000
SPMX 1001 0101 1111 1000
IN 1011 0 .. ..... .... @io_rd_imm
OUT 1011 1 .. ..... .... @io_rd_imm
PUSH 1001 001 rd:5 1111
POP 1001 000 rd:5 1111
XCH 1001 001 rd:5 0100
LAC 1001 001 rd:5 0110
LAS 1001 001 rd:5 0101
LAT 1001 001 rd:5 0111