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target/ppc: Don't use tcg_temp_local_new

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Since tcg_temp_new is now identical, use that.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-01-29 14:45:12 -10:00
parent 6180cc4027
commit 9723281fbb
3 changed files with 9 additions and 9 deletions
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6
target/ppc/translate.c
View file

@ -4415,7 +4415,7 @@ static void gen_bcond(DisasContext *ctx, int type)
TCGv target; TCGv target;
if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
target = tcg_temp_local_new(); target = tcg_temp_new();
if (type == BCOND_CTR) { if (type == BCOND_CTR) {
tcg_gen_mov_tl(target, cpu_ctr); tcg_gen_mov_tl(target, cpu_ctr);
} else if (type == BCOND_TAR) { } else if (type == BCOND_TAR) {
@ -5594,8 +5594,8 @@ static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
{ {
TCGv t0, t1; TCGv t0, t1;
t0 = tcg_temp_local_new(); t0 = tcg_temp_new();
t1 = tcg_temp_local_new(); t1 = tcg_temp_new();
switch (opc3 & 0x0D) { switch (opc3 & 0x0D) {
case 0x05: case 0x05:

8
target/ppc/translate/spe-impl.c.inc
View file

@ -168,7 +168,7 @@ static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{ {
TCGLabel *l1 = gen_new_label(); TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label(); TCGLabel *l2 = gen_new_label();
TCGv_i32 t0 = tcg_temp_local_new_i32(); TCGv_i32 t0 = tcg_temp_new_i32();
/* No error here: 6 bits are used */ /* No error here: 6 bits are used */
tcg_gen_andi_i32(t0, arg2, 0x3F); tcg_gen_andi_i32(t0, arg2, 0x3F);
@ -185,7 +185,7 @@ static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{ {
TCGLabel *l1 = gen_new_label(); TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label(); TCGLabel *l2 = gen_new_label();
TCGv_i32 t0 = tcg_temp_local_new_i32(); TCGv_i32 t0 = tcg_temp_new_i32();
/* No error here: 6 bits are used */ /* No error here: 6 bits are used */
tcg_gen_andi_i32(t0, arg2, 0x3F); tcg_gen_andi_i32(t0, arg2, 0x3F);
@ -202,7 +202,7 @@ static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{ {
TCGLabel *l1 = gen_new_label(); TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label(); TCGLabel *l2 = gen_new_label();
TCGv_i32 t0 = tcg_temp_local_new_i32(); TCGv_i32 t0 = tcg_temp_new_i32();
/* No error here: 6 bits are used */ /* No error here: 6 bits are used */
tcg_gen_andi_i32(t0, arg2, 0x3F); tcg_gen_andi_i32(t0, arg2, 0x3F);
@ -378,7 +378,7 @@ static inline void gen_evsel(DisasContext *ctx)
TCGLabel *l2 = gen_new_label(); TCGLabel *l2 = gen_new_label();
TCGLabel *l3 = gen_new_label(); TCGLabel *l3 = gen_new_label();
TCGLabel *l4 = gen_new_label(); TCGLabel *l4 = gen_new_label();
TCGv_i32 t0 = tcg_temp_local_new_i32(); TCGv_i32 t0 = tcg_temp_new_i32();
tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);

4
target/ppc/translate/vmx-impl.c.inc
View file

@ -1508,8 +1508,8 @@ static bool do_vcmpq(DisasContext *ctx, arg_VX_bf *a, bool sign)
REQUIRE_INSNS_FLAGS2(ctx, ISA310); REQUIRE_INSNS_FLAGS2(ctx, ISA310);
REQUIRE_VECTOR(ctx); REQUIRE_VECTOR(ctx);
vra = tcg_temp_local_new_i64(); vra = tcg_temp_new_i64();
vrb = tcg_temp_local_new_i64(); vrb = tcg_temp_new_i64();
gt = gen_new_label(); gt = gen_new_label();
lt = gen_new_label(); lt = gen_new_label();
done = gen_new_label(); done = gen_new_label();