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tcg: Merge INDEX_op_ctpop_{i32,i64}

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Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-08 18:37:43 -08:00
parent f8fa1dae3d
commit 97218ae918
7 changed files with 22 additions and 31 deletions
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6
docs/devel/tcg-ops.rst
View file

@ -366,12 +366,12 @@ Logical
- | *t0* = *t1* ? ctz(*t1*) : *t2* - | *t0* = *t1* ? ctz(*t1*) : *t2*
* - ctpop_i32/i64 *t0*, *t1* * - ctpop *t0*, *t1*
- | *t0* = number of bits set in *t1* - | *t0* = number of bits set in *t1*
| |
| With *ctpop* short for "count population", matching | The name *ctpop* is short for "count population", and matches
| the function name used in ``include/qemu/host-utils.h``. the function name used in ``include/qemu/host-utils.h``.
Shifts/Rotates Shifts/Rotates

3
include/tcg/tcg-opc.h
View file

@ -43,6 +43,7 @@ DEF(add, 1, 2, 0, TCG_OPF_INT)
DEF(and, 1, 2, 0, TCG_OPF_INT) DEF(and, 1, 2, 0, TCG_OPF_INT)
DEF(andc, 1, 2, 0, TCG_OPF_INT) DEF(andc, 1, 2, 0, TCG_OPF_INT)
DEF(clz, 1, 2, 0, TCG_OPF_INT) DEF(clz, 1, 2, 0, TCG_OPF_INT)
DEF(ctpop, 1, 1, 0, TCG_OPF_INT)
DEF(ctz, 1, 2, 0, TCG_OPF_INT) DEF(ctz, 1, 2, 0, TCG_OPF_INT)
DEF(divs, 1, 2, 0, TCG_OPF_INT) DEF(divs, 1, 2, 0, TCG_OPF_INT)
DEF(divs2, 2, 3, 0, TCG_OPF_INT) DEF(divs2, 2, 3, 0, TCG_OPF_INT)
@ -97,7 +98,6 @@ DEF(setcond2_i32, 1, 4, 1, 0)
DEF(bswap16_i32, 1, 1, 1, 0) DEF(bswap16_i32, 1, 1, 1, 0)
DEF(bswap32_i32, 1, 1, 1, 0) DEF(bswap32_i32, 1, 1, 1, 0)
DEF(ctpop_i32, 1, 1, 0, 0)
DEF(setcond_i64, 1, 2, 1, 0) DEF(setcond_i64, 1, 2, 1, 0)
DEF(negsetcond_i64, 1, 2, 1, 0) DEF(negsetcond_i64, 1, 2, 1, 0)
@ -130,7 +130,6 @@ DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
DEF(bswap16_i64, 1, 1, 1, 0) DEF(bswap16_i64, 1, 1, 1, 0)
DEF(bswap32_i64, 1, 1, 1, 0) DEF(bswap32_i64, 1, 1, 1, 0)
DEF(bswap64_i64, 1, 1, 1, 0) DEF(bswap64_i64, 1, 1, 1, 0)
DEF(ctpop_i64, 1, 1, 0, 0)
DEF(add2_i64, 2, 4, 0, 0) DEF(add2_i64, 2, 4, 0, 0)
DEF(sub2_i64, 2, 4, 0, 0) DEF(sub2_i64, 2, 4, 0, 0)

9
tcg/optimize.c
View file

@ -515,11 +515,8 @@ static uint64_t do_constant_folding_2(TCGOpcode op, TCGType type,
} }
return x ? ctz64(x) : y; return x ? ctz64(x) : y;
case INDEX_op_ctpop_i32: case INDEX_op_ctpop:
return ctpop32(x); return type == TCG_TYPE_I32 ? ctpop32(x) : ctpop64(x);
case INDEX_op_ctpop_i64:
return ctpop64(x);
CASE_OP_32_64(bswap16): CASE_OP_32_64(bswap16):
x = bswap16(x); x = bswap16(x);
@ -2902,7 +2899,7 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_ctz: case INDEX_op_ctz:
done = fold_count_zeros(&ctx, op); done = fold_count_zeros(&ctx, op);
break; break;
CASE_OP_32_64(ctpop): case INDEX_op_ctpop:
done = fold_ctpop(&ctx, op); done = fold_ctpop(&ctx, op);
break; break;
CASE_OP_32_64(deposit): CASE_OP_32_64(deposit):

21
tcg/tcg-op.c
View file

@ -765,8 +765,7 @@ void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
tcg_temp_free_i64(t2); tcg_temp_free_i64(t2);
return; return;
} }
if (tcg_op_supported(INDEX_op_ctpop_i32, TCG_TYPE_I32, 0) || if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_REG, 0)) {
tcg_op_supported(INDEX_op_ctpop_i64, TCG_TYPE_I64, 0)) {
t = tcg_temp_ebb_new_i32(); t = tcg_temp_ebb_new_i32();
tcg_gen_subi_i32(t, arg1, 1); tcg_gen_subi_i32(t, arg1, 1);
tcg_gen_andc_i32(t, t, arg1); tcg_gen_andc_i32(t, t, arg1);
@ -791,7 +790,7 @@ void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2)
{ {
if (arg2 == 32 if (arg2 == 32
&& !tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I32, 0) && !tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I32, 0)
&& tcg_op_supported(INDEX_op_ctpop_i32, TCG_TYPE_I32, 0)) { && tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_REG, 0)) {
/* This equivalence has the advantage of not requiring a fixup. */ /* This equivalence has the advantage of not requiring a fixup. */
TCGv_i32 t = tcg_temp_ebb_new_i32(); TCGv_i32 t = tcg_temp_ebb_new_i32();
tcg_gen_subi_i32(t, arg1, 1); tcg_gen_subi_i32(t, arg1, 1);
@ -819,9 +818,9 @@ void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg)
void tcg_gen_ctpop_i32(TCGv_i32 ret, TCGv_i32 arg1) void tcg_gen_ctpop_i32(TCGv_i32 ret, TCGv_i32 arg1)
{ {
if (tcg_op_supported(INDEX_op_ctpop_i32, TCG_TYPE_I32, 0)) { if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I32, 0)) {
tcg_gen_op2_i32(INDEX_op_ctpop_i32, ret, arg1); tcg_gen_op2_i32(INDEX_op_ctpop, ret, arg1);
} else if (tcg_op_supported(INDEX_op_ctpop_i64, TCG_TYPE_I64, 0)) { } else if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I64, 0)) {
TCGv_i64 t = tcg_temp_ebb_new_i64(); TCGv_i64 t = tcg_temp_ebb_new_i64();
tcg_gen_extu_i32_i64(t, arg1); tcg_gen_extu_i32_i64(t, arg1);
tcg_gen_ctpop_i64(t, t); tcg_gen_ctpop_i64(t, t);
@ -2372,7 +2371,7 @@ void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
tcg_gen_op3_i64(INDEX_op_ctz, ret, arg1, arg2); tcg_gen_op3_i64(INDEX_op_ctz, ret, arg1, arg2);
return; return;
} }
if (tcg_op_supported(INDEX_op_ctpop_i64, TCG_TYPE_I64, 0)) { if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I64, 0)) {
t = tcg_temp_ebb_new_i64(); t = tcg_temp_ebb_new_i64();
tcg_gen_subi_i64(t, arg1, 1); tcg_gen_subi_i64(t, arg1, 1);
tcg_gen_andc_i64(t, t, arg1); tcg_gen_andc_i64(t, t, arg1);
@ -2406,7 +2405,7 @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
tcg_temp_free_i32(t32); tcg_temp_free_i32(t32);
} else if (arg2 == 64 } else if (arg2 == 64
&& !tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I64, 0) && !tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I64, 0)
&& tcg_op_supported(INDEX_op_ctpop_i64, TCG_TYPE_I64, 0)) { && tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I64, 0)) {
/* This equivalence has the advantage of not requiring a fixup. */ /* This equivalence has the advantage of not requiring a fixup. */
TCGv_i64 t = tcg_temp_ebb_new_i64(); TCGv_i64 t = tcg_temp_ebb_new_i64();
tcg_gen_subi_i64(t, arg1, 1); tcg_gen_subi_i64(t, arg1, 1);
@ -2435,12 +2434,12 @@ void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg)
void tcg_gen_ctpop_i64(TCGv_i64 ret, TCGv_i64 arg1) void tcg_gen_ctpop_i64(TCGv_i64 ret, TCGv_i64 arg1)
{ {
if (TCG_TARGET_REG_BITS == 64) { if (TCG_TARGET_REG_BITS == 64) {
if (tcg_op_supported(INDEX_op_ctpop_i64, TCG_TYPE_I64, 0)) { if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I64, 0)) {
tcg_gen_op2_i64(INDEX_op_ctpop_i64, ret, arg1); tcg_gen_op2_i64(INDEX_op_ctpop, ret, arg1);
return; return;
} }
} else { } else {
if (tcg_op_supported(INDEX_op_ctpop_i32, TCG_TYPE_I32, 0)) { if (tcg_op_supported(INDEX_op_ctpop, TCG_TYPE_I32, 0)) {
tcg_gen_ctpop_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1)); tcg_gen_ctpop_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1));
tcg_gen_ctpop_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); tcg_gen_ctpop_i32(TCGV_LOW(ret), TCGV_LOW(arg1));
tcg_gen_add_i32(TCGV_LOW(ret), TCGV_LOW(ret), TCGV_HIGH(ret)); tcg_gen_add_i32(TCGV_LOW(ret), TCGV_LOW(ret), TCGV_HIGH(ret));

6
tcg/tcg.c
View file

@ -1027,8 +1027,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_and, TCGOutOpBinary, outop_and), OUTOP(INDEX_op_and, TCGOutOpBinary, outop_and),
OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc), OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
OUTOP(INDEX_op_clz, TCGOutOpBinary, outop_clz), OUTOP(INDEX_op_clz, TCGOutOpBinary, outop_clz),
OUTOP(INDEX_op_ctpop_i32, TCGOutOpUnary, outop_ctpop), OUTOP(INDEX_op_ctpop, TCGOutOpUnary, outop_ctpop),
OUTOP(INDEX_op_ctpop_i64, TCGOutOpUnary, outop_ctpop),
OUTOP(INDEX_op_ctz, TCGOutOpBinary, outop_ctz), OUTOP(INDEX_op_ctz, TCGOutOpBinary, outop_ctz),
OUTOP(INDEX_op_divs, TCGOutOpBinary, outop_divs), OUTOP(INDEX_op_divs, TCGOutOpBinary, outop_divs),
OUTOP(INDEX_op_divu, TCGOutOpBinary, outop_divu), OUTOP(INDEX_op_divu, TCGOutOpBinary, outop_divu),
@ -5447,8 +5446,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
} }
break; break;
case INDEX_op_ctpop_i32: case INDEX_op_ctpop:
case INDEX_op_ctpop_i64:
case INDEX_op_neg: case INDEX_op_neg:
case INDEX_op_not: case INDEX_op_not:
{ {

6
tcg/tci.c
View file

@ -577,8 +577,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rr(insn, &r0, &r1); tci_args_rr(insn, &r0, &r1);
regs[r0] = ~regs[r1]; regs[r0] = ~regs[r1];
break; break;
case INDEX_op_ctpop_i32: case INDEX_op_ctpop:
case INDEX_op_ctpop_i64:
tci_args_rr(insn, &r0, &r1); tci_args_rr(insn, &r0, &r1);
regs[r0] = ctpop_tr(regs[r1]); regs[r0] = ctpop_tr(regs[r1]);
break; break;
@ -1023,6 +1022,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
op_name, str_r(r0), str_r(r1), s2); op_name, str_r(r0), str_r(r1), s2);
break; break;
case INDEX_op_ctpop:
case INDEX_op_mov: case INDEX_op_mov:
case INDEX_op_neg: case INDEX_op_neg:
case INDEX_op_not: case INDEX_op_not:
@ -1033,8 +1033,6 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_bswap32_i32: case INDEX_op_bswap32_i32:
case INDEX_op_bswap32_i64: case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64: case INDEX_op_bswap64_i64:
case INDEX_op_ctpop_i32:
case INDEX_op_ctpop_i64:
tci_args_rr(insn, &r0, &r1); tci_args_rr(insn, &r0, &r1);
info->fprintf_func(info->stream, "%-12s %s, %s", info->fprintf_func(info->stream, "%-12s %s, %s",
op_name, str_r(r0), str_r(r1)); op_name, str_r(r0), str_r(r1));

2
tcg/tci/tcg-target.c.inc
View file

@ -883,7 +883,7 @@ static const TCGOutOpBinary outop_xor = {
static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{ {
tcg_out_op_rr(s, glue(INDEX_op_ctpop_i,TCG_TARGET_REG_BITS), a0, a1); tcg_out_op_rr(s, INDEX_op_ctpop, a0, a1);
} }
static TCGConstraintSetIndex cset_ctpop(TCGType type, unsigned flags) static TCGConstraintSetIndex cset_ctpop(TCGType type, unsigned flags)