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ppc patch queue 2017-12-15

Browse source 
First pull request for qemu-2.12.  This has quite a bit of stuff
 accumulated while 2.11 was finalizing.  Highlights are:
 
   * Some preliminary work towards implementing the "XIVE" POWER9
     interrupt controller
   * Some fixes for problems during reboot with MTTCG
   * A substantial TCG performance improvement via
     tcg_get_lookup_and_goto_ptr
   * Numerous assorted cleanups and bugfixes that weren't urgent enough
     for 2.11
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEdfRlhq5hpmzETofcbDjKyiDZs5IFAlozPgQACgkQbDjKyiDZ
 s5JX9xAAn0hq40aioa9NYREFIbcp6GBgzt4UEMNGtHYSzEkjYhBClxhdRWW//sJA
 ahXhuDj6Af2tNG/oyIxZrS/iocv+ibodRfs5++V8mKK7PSIGxx5qK+PCOz88/BKs
 DPgU5yBSiZwtAocJnVIW6jNm6niqhpeIknOaf2ugbcvxRYGbBlWus9vJmsp+wGq5
 Ing5loe92nle0dsMNxwfDptSnLw2G/0Kni/of6Tic/NkvGEjlA/hG4y5xXwGYsuD
 d3Ub5TTCN7VoRgDFGve6HwH79m5U34P01s0/ZuwykeC16U3R58TOWQ5urhb6DEeT
 Z4Q9+5OHtj6e4kW8zUUlxWSUJ87kdYCW21j+MlzRV1K6b+dyKC7TB9Ve7qp6r1jp
 Qvpojx1RstjBSJPCJRsu8nK9dVIfD3T/ibLb7EMDGCA9dW2qT8QxhGvOs75KxXby
 qhayXW27Q/UdOx0e91Nnj2bYj4tmLrAz2YEFQabq+Z9QvCQwHCtrQeuyb/cV7ri1
 Njsrs7Fuz9G4xrFeWCC8V3WTrrij3ukPEHO7+Yjuu0e2CXAjaBtPsnp8zUE1wd36
 Q/dDmC46YLgrX/XIJfq6P3Fsibv2+Ppm9pPXcfCJZQ006WtVTBPVkOfAApb/cAR5
 jM+samFYbRhOT899+8wbCgslMVBNTnM4dGEXJOs32OltIsO97zI=
 =7qyZ
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.12-20171215' into staging

ppc patch queue 2017-12-15

First pull request for qemu-2.12.  This has quite a bit of stuff
accumulated while 2.11 was finalizing.  Highlights are:

  * Some preliminary work towards implementing the "XIVE" POWER9
    interrupt controller
  * Some fixes for problems during reboot with MTTCG
  * A substantial TCG performance improvement via
    tcg_get_lookup_and_goto_ptr
  * Numerous assorted cleanups and bugfixes that weren't urgent enough
    for 2.11

# gpg: Signature made Fri 15 Dec 2017 03:14:12 GMT
# gpg:                using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>"
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>"
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>"
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.12-20171215: (24 commits)
  spapr: don't initialize PATB entry if max-cpu-compat < power9
  spapr: Assume msi_nonbroken
  spapr: Rename machine init functions for clarity
  target/ppc: introduce the PPC_BIT() macro
  spapr_events: drop bogus cell from "interrupt-ranges" property
  spapr: fix LSI interrupt specifiers in the device tree
  spapr: replace numa_get_node() with lookup in pc-dimm list
  spapr: introduce a spapr_qirq() helper
  spapr: introduce a spapr_irq_set_lsi() helper
  spapr: move the IRQ allocation routines under the machine
  ppc/xics: assign of the CPU 'intc' pointer under the core
  ppc/xics: introduce an icp_create() helper
  spapr/rtas: do not reset the MSR in stop-self command
  spapr/rtas: fix reboot of a a SMP TCG guest
  spapr/rtas: disable the decrementer interrupt when a CPU is unplugged
  e500: fix pci host bridge class/type
  openpic: debug w/ info_report()
  pcc: define the Power-saving mode Exit Cause Enable bits in PowerPCCPUClass
  nvram: add AT24Cx i2c eeprom
  e500: name openpic and pci host bridge
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2017-12-15 11:13:43 +00:00
commit 96a6298889
29 changed files with 638 additions and 469 deletions
Download patch file Download diff file Expand all files Collapse all files

2
include/hw/compat.h
View file

@ -1,6 +1,8 @@
#ifndef HW_COMPAT_H
#define HW_COMPAT_H
#define HW_COMPAT_2_11
#define HW_COMPAT_2_10 \
{\
.driver = "virtio-mouse-device",\

2
include/hw/pci-host/spapr.h
View file

@ -108,7 +108,7 @@ static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
{
sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
return xics_get_qirq(XICS_FABRIC(spapr), phb->lsi_table[pin].irq);
return spapr_qirq(spapr, phb->lsi_table[pin].irq);
}
PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index);

17
include/hw/ppc/spapr.h
View file

@ -590,6 +590,16 @@ void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr);
#define RTAS_EVENT_SCAN_RATE 1
/* This helper should be used to encode interrupt specifiers when the related
* "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie,
* VIO devices, RTAS event sources and PHBs).
*/
static inline void spapr_dt_xics_irq(uint32_t *intspec, int irq, bool is_lsi)
{
intspec[0] = cpu_to_be32(irq);
intspec[1] = is_lsi ? cpu_to_be32(1) : 0;
}
typedef struct sPAPRTCETable sPAPRTCETable;
#define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
@ -707,4 +717,11 @@ void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
int spapr_vcpu_id(PowerPCCPU *cpu);
PowerPCCPU *spapr_find_cpu(int vcpu_id);
int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi,
Error **errp);
int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi,
bool align, Error **errp);
void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num);
qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq);
#endif /* HW_SPAPR_H */

2
include/hw/ppc/spapr_cpu_core.h
View file

@ -28,7 +28,7 @@ typedef struct sPAPRCPUCore {
CPUCore parent_obj;
/*< public >*/
void *threads;
PowerPCCPU **threads;
int node_id;
} sPAPRCPUCore;

2
include/hw/ppc/spapr_vio.h
View file

@ -87,7 +87,7 @@ static inline qemu_irq spapr_vio_qirq(VIOsPAPRDevice *dev)
{
sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
return xics_get_qirq(XICS_FABRIC(spapr), dev->irq);
return spapr_qirq(spapr, dev->irq);
}
static inline bool spapr_vio_dma_valid(VIOsPAPRDevice *dev, uint64_t taddr,

8
include/hw/ppc/xics.h
View file

@ -181,13 +181,8 @@ typedef struct XICSFabricClass {
#define XICS_IRQS_SPAPR 1024
int spapr_ics_alloc(ICSState *ics, int irq_hint, bool lsi, Error **errp);
int spapr_ics_alloc_block(ICSState *ics, int num, bool lsi, bool align,
Error **errp);
void spapr_ics_free(ICSState *ics, int irq, int num);
void spapr_dt_xics(int nr_servers, void *fdt, uint32_t phandle);
qemu_irq xics_get_qirq(XICSFabric *xi, int irq);
ICPState *xics_icp_get(XICSFabric *xi, int server);
/* Internal XICS interfaces */
@ -212,4 +207,7 @@ typedef struct sPAPRMachineState sPAPRMachineState;
int xics_kvm_init(sPAPRMachineState *spapr, Error **errp);
void xics_spapr_init(sPAPRMachineState *spapr);
Object *icp_create(Object *cpu, const char *type, XICSFabric *xi,
Error **errp);
#endif /* XICS_H */

10
include/sysemu/numa.h
View file

@ -10,17 +10,10 @@
extern int nb_numa_nodes; /* Number of NUMA nodes */
extern bool have_numa_distance;
struct numa_addr_range {
ram_addr_t mem_start;
ram_addr_t mem_end;
QLIST_ENTRY(numa_addr_range) entry;
};
struct node_info {
uint64_t node_mem;
struct HostMemoryBackend *node_memdev;
bool present;
QLIST_HEAD(, numa_addr_range) addr; /* List to store address ranges */
uint8_t distance[MAX_NODES];
};
@ -33,9 +26,6 @@ extern NodeInfo numa_info[MAX_NODES];
void parse_numa_opts(MachineState *ms);
void query_numa_node_mem(NumaNodeMem node_mem[]);
extern QemuOptsList qemu_numa_opts;
void numa_set_mem_node_id(ram_addr_t addr, uint64_t size, uint32_t node);
void numa_unset_mem_node_id(ram_addr_t addr, uint64_t size, uint32_t node);
uint32_t numa_get_node(ram_addr_t addr, Error **errp);
void numa_legacy_auto_assign_ram(MachineClass *mc, NodeInfo *nodes,
int nb_nodes, ram_addr_t size);
void numa_default_auto_assign_ram(MachineClass *mc, NodeInfo *nodes,