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target/arm: Implement SVE Integer Multiply-Add Group

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-05-18 17:48:08 +01:00 • committed by Peter Maydell
parent afac6d0467
commit 96a36e4a44
4 changed files with 126 additions and 0 deletions
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34
target/arm/translate-sve.c
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@ -634,6 +634,40 @@ DO_ZPZW(LSL, lsl)
#undef DO_ZPZW
/*
*** SVE Integer Multiply-Add Group
*/
static bool do_zpzzz_ool(DisasContext *s, arg_rprrr_esz *a,
gen_helper_gvec_5 *fn)
{
if (sve_access_check(s)) {
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_5_ool(vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->ra),
vec_full_reg_offset(s, a->rn),
vec_full_reg_offset(s, a->rm),
pred_full_reg_offset(s, a->pg),
vsz, vsz, 0, fn);
}
return true;
}
#define DO_ZPZZZ(NAME, name) \
static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a, uint32_t insn) \
{ \
static gen_helper_gvec_5 * const fns[4] = { \
gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \
gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \
}; \
return do_zpzzz_ool(s, a, fns[a->esz]); \
}
DO_ZPZZZ(MLA, mla)
DO_ZPZZZ(MLS, mls)
#undef DO_ZPZZZ
/*
*** SVE Predicate Logical Operations Group
*/