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ppc/xive2: Add support for MMIO operations on the NVPG/NVC BAR
Add support for the NVPG and NVC BARs. Access to the BAR pages will cause backlog counter operations to either increment or decriment the counter. Also added qtests for the same. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Frederic Barrat
Nicholas Piggin
parent
c2b7fade9f
commit
96a2132ce9
9 changed files with 328 additions and 15 deletions
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@ -2202,21 +2202,40 @@ static const MemoryRegionOps pnv_xive2_tm_ops = {
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},
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};
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static uint64_t pnv_xive2_nvc_read(void *opaque, hwaddr offset,
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static uint64_t pnv_xive2_nvc_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvXive2 *xive = PNV_XIVE2(opaque);
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XivePresenter *xptr = XIVE_PRESENTER(xive);
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uint32_t page = addr >> xive->nvpg_shift;
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uint16_t op = addr & 0xFFF;
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uint8_t blk = pnv_xive2_block_id(xive);
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xive2_error(xive, "NVC: invalid read @%"HWADDR_PRIx, offset);
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return -1;
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if (size != 2) {
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qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid nvc load size %d\n",
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size);
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return -1;
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}
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return xive2_presenter_nvgc_backlog_op(xptr, true, blk, page, op, 1);
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}
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static void pnv_xive2_nvc_write(void *opaque, hwaddr offset,
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static void pnv_xive2_nvc_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvXive2 *xive = PNV_XIVE2(opaque);
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XivePresenter *xptr = XIVE_PRESENTER(xive);
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uint32_t page = addr >> xive->nvc_shift;
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uint16_t op = addr & 0xFFF;
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uint8_t blk = pnv_xive2_block_id(xive);
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xive2_error(xive, "NVC: invalid write @%"HWADDR_PRIx, offset);
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if (size != 1) {
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qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid nvc write size %d\n",
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size);
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return;
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}
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(void)xive2_presenter_nvgc_backlog_op(xptr, true, blk, page, op, val);
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}
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static const MemoryRegionOps pnv_xive2_nvc_ops = {
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@ -2224,30 +2243,63 @@ static const MemoryRegionOps pnv_xive2_nvc_ops = {
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.write = pnv_xive2_nvc_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.valid = {
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.min_access_size = 8,
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.min_access_size = 1,
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.max_access_size = 8,
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},
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.impl = {
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.min_access_size = 8,
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.min_access_size = 1,
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.max_access_size = 8,
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},
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};
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static uint64_t pnv_xive2_nvpg_read(void *opaque, hwaddr offset,
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static uint64_t pnv_xive2_nvpg_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvXive2 *xive = PNV_XIVE2(opaque);
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XivePresenter *xptr = XIVE_PRESENTER(xive);
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uint32_t page = addr >> xive->nvpg_shift;
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uint16_t op = addr & 0xFFF;
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uint32_t index = page >> 1;
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uint8_t blk = pnv_xive2_block_id(xive);
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xive2_error(xive, "NVPG: invalid read @%"HWADDR_PRIx, offset);
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return -1;
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if (size != 2) {
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qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid nvpg load size %d\n",
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size);
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return -1;
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}
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if (page % 2) {
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/* odd page - NVG */
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return xive2_presenter_nvgc_backlog_op(xptr, false, blk, index, op, 1);
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} else {
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/* even page - NVP */
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return xive2_presenter_nvp_backlog_op(xptr, blk, index, op);
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}
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}
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static void pnv_xive2_nvpg_write(void *opaque, hwaddr offset,
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static void pnv_xive2_nvpg_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvXive2 *xive = PNV_XIVE2(opaque);
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XivePresenter *xptr = XIVE_PRESENTER(xive);
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uint32_t page = addr >> xive->nvpg_shift;
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uint16_t op = addr & 0xFFF;
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uint32_t index = page >> 1;
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uint8_t blk = pnv_xive2_block_id(xive);
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xive2_error(xive, "NVPG: invalid write @%"HWADDR_PRIx, offset);
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if (size != 1) {
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qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid nvpg write size %d\n",
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size);
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return;
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}
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if (page % 2) {
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/* odd page - NVG */
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(void)xive2_presenter_nvgc_backlog_op(xptr, false, blk, index, op, val);
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} else {
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/* even page - NVP */
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(void)xive2_presenter_nvp_backlog_op(xptr, blk, index, op);
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}
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}
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static const MemoryRegionOps pnv_xive2_nvpg_ops = {
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@ -2255,11 +2307,11 @@ static const MemoryRegionOps pnv_xive2_nvpg_ops = {
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.write = pnv_xive2_nvpg_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.valid = {
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.min_access_size = 8,
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.min_access_size = 1,
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.max_access_size = 8,
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},
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.impl = {
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.min_access_size = 8,
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.min_access_size = 1,
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.max_access_size = 8,
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},
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};
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@ -286,6 +286,10 @@ xive_tctx_tm_read(uint32_t index, uint64_t offset, unsigned int size, uint64_t v
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xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring, uint8_t group_level) "found NVT 0x%x/0x%x ring=0x%x group_level=%d"
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xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) "END 0x%x/0x%x @0x%"PRIx64
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# xive2.c
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xive_nvp_backlog_op(uint8_t blk, uint32_t idx, uint8_t op, uint8_t priority, uint8_t rc) "NVP 0x%x/0x%x operation=%d priority=%d rc=%d"
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xive_nvgc_backlog_op(bool c, uint8_t blk, uint32_t idx, uint8_t op, uint8_t priority, uint32_t rc) "NVGC crowd=%d 0x%x/0x%x operation=%d priority=%d rc=%d"
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# pnv_xive.c
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pnv_xive_ic_hw_trigger(uint64_t addr, uint64_t val) "@0x%"PRIx64" val=0x%"PRIx64
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@ -88,6 +88,93 @@ static void xive2_nvgc_set_backlog(Xive2Nvgc *nvgc, uint8_t priority,
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}
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}
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uint64_t xive2_presenter_nvgc_backlog_op(XivePresenter *xptr,
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bool crowd,
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uint8_t blk, uint32_t idx,
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uint16_t offset, uint16_t val)
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{
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Xive2Router *xrtr = XIVE2_ROUTER(xptr);
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uint8_t priority = GETFIELD(NVx_BACKLOG_PRIO, offset);
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uint8_t op = GETFIELD(NVx_BACKLOG_OP, offset);
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Xive2Nvgc nvgc;
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uint32_t count, old_count;
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if (xive2_router_get_nvgc(xrtr, crowd, blk, idx, &nvgc)) {
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qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No %s %x/%x\n",
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crowd ? "NVC" : "NVG", blk, idx);
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return -1;
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}
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if (!xive2_nvgc_is_valid(&nvgc)) {
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qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVG %x/%x\n", blk, idx);
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return -1;
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}
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old_count = xive2_nvgc_get_backlog(&nvgc, priority);
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count = old_count;
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/*
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* op:
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* 0b00 => increment
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* 0b01 => decrement
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* 0b1- => read
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*/
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if (op == 0b00 || op == 0b01) {
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if (op == 0b00) {
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count += val;
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} else {
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if (count > val) {
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count -= val;
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} else {
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count = 0;
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}
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}
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xive2_nvgc_set_backlog(&nvgc, priority, count);
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xive2_router_write_nvgc(xrtr, crowd, blk, idx, &nvgc);
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}
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trace_xive_nvgc_backlog_op(crowd, blk, idx, op, priority, old_count);
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return old_count;
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}
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uint64_t xive2_presenter_nvp_backlog_op(XivePresenter *xptr,
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uint8_t blk, uint32_t idx,
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uint16_t offset)
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{
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Xive2Router *xrtr = XIVE2_ROUTER(xptr);
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uint8_t priority = GETFIELD(NVx_BACKLOG_PRIO, offset);
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uint8_t op = GETFIELD(NVx_BACKLOG_OP, offset);
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Xive2Nvp nvp;
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uint8_t ipb, old_ipb, rc;
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if (xive2_router_get_nvp(xrtr, blk, idx, &nvp)) {
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qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", blk, idx);
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return -1;
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}
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if (!xive2_nvp_is_valid(&nvp)) {
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qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVP %x/%x\n", blk, idx);
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return -1;
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}
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old_ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2);
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ipb = old_ipb;
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/*
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* op:
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* 0b00 => set priority bit
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* 0b01 => reset priority bit
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* 0b1- => read
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*/
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if (op == 0b00 || op == 0b01) {
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if (op == 0b00) {
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ipb |= xive_priority_to_ipb(priority);
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} else {
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ipb &= ~xive_priority_to_ipb(priority);
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}
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nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb);
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xive2_router_write_nvp(xrtr, blk, idx, &nvp, 2);
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}
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rc = !!(old_ipb & xive_priority_to_ipb(priority));
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trace_xive_nvp_backlog_op(blk, idx, op, priority, rc);
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return rc;
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}
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void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf)
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{
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if (!xive2_eas_is_valid(eas)) {
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