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target/riscv: Implement Ssdbltrp exception handling

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When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode
while SSTATUS.SDT isn't cleared, generate a double trap exception to
M-mode.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250110125441.3208676-5-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Clément Léger 2025-01-10 13:54:35 +01:00 • committed by Alistair Francis
parent 72d71d8732
commit 967760f62c
3 changed files with 39 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

2
target/riscv/cpu.c
View file

@ -303,7 +303,7 @@ static const char * const riscv_excp_names[] = {
"load_page_fault",
"reserved",
"store_page_fault",
"reserved",
"double_trap",
"reserved",
"reserved",
"reserved",

1
target/riscv/cpu_bits.h
View file

@ -701,6 +701,7 @@ typedef enum RISCVException {
RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
RISCV_EXCP_DOUBLE_TRAP = 0x10,
RISCV_EXCP_SW_CHECK = 0x12, /* since: priv-1.13.0 */
RISCV_EXCP_HW_ERR = 0x13, /* since: priv-1.13.0 */
RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,

42
target/riscv/cpu_helper.c
View file

@ -1951,6 +1951,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
bool virt = env->virt_enabled;
bool write_gva = false;
bool always_storeamo = (env->excp_uw2 & RISCV_UW2_ALWAYS_STORE_AMO);
bool vsmode_exc;
uint64_t s;
int mode;
@ -1965,6 +1966,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
!(env->mip & (1ULL << cause));
bool vs_injected = env->hvip & (1ULL << cause) & env->hvien &&
!(env->mip & (1ULL << cause));
bool smode_double_trap = false;
uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
target_ulong tval = 0;
target_ulong tinst = 0;
target_ulong htval = 0;
@ -2088,6 +2091,30 @@ void riscv_cpu_do_interrupt(CPUState *cs)
mode = env->priv <= PRV_S && cause < 64 &&
(((deleg >> cause) & 1) || s_injected || vs_injected) ? PRV_S : PRV_M;
vsmode_exc = env->virt_enabled && (((hdeleg >> cause) & 1) || vs_injected);
/*
* Check double trap condition only if already in S-mode and targeting
* S-mode
*/
if (cpu->cfg.ext_ssdbltrp && env->priv == PRV_S && mode == PRV_S) {
bool dte = (env->menvcfg & MENVCFG_DTE) != 0;
bool sdt = (env->mstatus & MSTATUS_SDT) != 0;
/* In VS or HS */
if (riscv_has_ext(env, RVH)) {
if (vsmode_exc) {
/* VS -> VS, use henvcfg instead of menvcfg*/
dte = (env->henvcfg & HENVCFG_DTE) != 0;
} else if (env->virt_enabled) {
/* VS -> HS, use mstatus_hs */
sdt = (env->mstatus_hs & MSTATUS_SDT) != 0;
}
}
smode_double_trap = dte && sdt;
if (smode_double_trap) {
mode = PRV_M;
}
}
if (mode == PRV_S) {
/* handle the trap in S-mode */
/* save elp status */
@ -2096,10 +2123,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
}
if (riscv_has_ext(env, RVH)) {
uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
if (env->virt_enabled &&
(((hdeleg >> cause) & 1) || vs_injected)) {
if (vsmode_exc) {
/* Trap to VS mode */
/*
* See if we need to adjust cause. Yes if its VS mode interrupt
@ -2132,6 +2156,9 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
if (riscv_env_smode_dbltrp_enabled(env, virt)) {
s = set_field(s, MSTATUS_SDT, 1);
}
env->mstatus = s;
sxlen = 16 << riscv_cpu_sxl(env);
env->scause = cause | ((target_ulong)async << (sxlen - 1));
@ -2184,9 +2211,14 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_MIE, 0);
env->mstatus = s;
env->mcause = cause | ((target_ulong)async << (mxlen - 1));
if (smode_double_trap) {
env->mtval2 = env->mcause;
env->mcause = RISCV_EXCP_DOUBLE_TRAP;
} else {
env->mtval2 = mtval2;
}
env->mepc = env->pc;
env->mtval = tval;
env->mtval2 = mtval2;
env->mtinst = tinst;
/*