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https://github.com/Motorhead1991/qemu.git
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ioapic: convert to qdev
Convert to qdev. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
parent
7d0500c49a
commit
9605111958
4 changed files with 51 additions and 19 deletions
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@ -1,7 +1,6 @@
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#ifndef APIC_H
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#ifndef APIC_H
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#define APIC_H
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#define APIC_H
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typedef struct IOAPICState IOAPICState;
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void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
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void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
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uint8_t delivery_mode,
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uint8_t delivery_mode,
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uint8_t vector_num, uint8_t polarity,
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uint8_t vector_num, uint8_t polarity,
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@ -10,7 +9,6 @@ int apic_init(CPUState *env);
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int apic_accept_pic_intr(CPUState *env);
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int apic_accept_pic_intr(CPUState *env);
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void apic_deliver_pic_intr(CPUState *env, int level);
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void apic_deliver_pic_intr(CPUState *env, int level);
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int apic_get_interrupt(CPUState *env);
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int apic_get_interrupt(CPUState *env);
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qemu_irq *ioapic_init(void);
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void apic_reset_irq_delivered(void);
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void apic_reset_irq_delivered(void);
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int apic_get_irq_delivered(void);
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int apic_get_irq_delivered(void);
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45
hw/ioapic.c
45
hw/ioapic.c
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@ -25,6 +25,7 @@
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#include "apic.h"
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#include "apic.h"
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#include "qemu-timer.h"
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#include "qemu-timer.h"
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#include "host-utils.h"
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#include "host-utils.h"
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#include "sysbus.h"
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//#define DEBUG_IOAPIC
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//#define DEBUG_IOAPIC
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@ -35,7 +36,6 @@
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#define DPRINTF(fmt, ...)
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#define DPRINTF(fmt, ...)
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#endif
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#endif
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#define IOAPIC_NUM_PINS 0x18
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#define IOAPIC_LVT_MASKED (1<<16)
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#define IOAPIC_LVT_MASKED (1<<16)
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#define IOAPIC_TRIGGER_EDGE 0
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#define IOAPIC_TRIGGER_EDGE 0
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@ -50,7 +50,10 @@
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#define IOAPIC_DM_SIPI 0x5
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#define IOAPIC_DM_SIPI 0x5
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#define IOAPIC_DM_EXTINT 0x7
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#define IOAPIC_DM_EXTINT 0x7
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typedef struct IOAPICState IOAPICState;
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struct IOAPICState {
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struct IOAPICState {
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SysBusDevice busdev;
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uint8_t id;
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uint8_t id;
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uint8_t ioregsel;
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uint8_t ioregsel;
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@ -209,12 +212,14 @@ static const VMStateDescription vmstate_ioapic = {
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}
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}
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};
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};
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static void ioapic_reset(void *opaque)
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static void ioapic_reset(DeviceState *d)
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{
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{
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IOAPICState *s = opaque;
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IOAPICState *s = DO_UPCAST(IOAPICState, busdev.qdev, d);
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int i;
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int i;
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memset(s, 0, sizeof(*s));
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s->id = 0;
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s->ioregsel = 0;
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s->irr = 0;
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for(i = 0; i < IOAPIC_NUM_PINS; i++)
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for(i = 0; i < IOAPIC_NUM_PINS; i++)
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s->ioredtbl[i] = 1 << 16; /* mask LVT */
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s->ioredtbl[i] = 1 << 16; /* mask LVT */
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}
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}
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@ -231,22 +236,32 @@ static CPUWriteMemoryFunc * const ioapic_mem_write[3] = {
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ioapic_mem_writel,
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ioapic_mem_writel,
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};
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};
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qemu_irq *ioapic_init(void)
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static int ioapic_init1(SysBusDevice *dev)
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{
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{
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IOAPICState *s;
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IOAPICState *s = FROM_SYSBUS(IOAPICState, dev);
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qemu_irq *irq;
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int io_memory;
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int io_memory;
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s = qemu_mallocz(sizeof(IOAPICState));
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ioapic_reset(s);
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io_memory = cpu_register_io_memory(ioapic_mem_read,
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io_memory = cpu_register_io_memory(ioapic_mem_read,
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ioapic_mem_write, s);
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ioapic_mem_write, s);
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cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
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sysbus_init_mmio(dev, 0x1000, io_memory);
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vmstate_register(0, &vmstate_ioapic, s);
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qdev_init_gpio_in(&dev->qdev, ioapic_set_irq, IOAPIC_NUM_PINS);
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qemu_register_reset(ioapic_reset, s);
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irq = qemu_allocate_irqs(ioapic_set_irq, s, IOAPIC_NUM_PINS);
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return irq;
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return 0;
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}
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}
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static SysBusDeviceInfo ioapic_info = {
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.init = ioapic_init1,
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.qdev.name = "ioapic",
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.qdev.size = sizeof(IOAPICState),
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.qdev.vmsd = &vmstate_ioapic,
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.qdev.reset = ioapic_reset,
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.qdev.no_user = 1,
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};
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static void ioapic_register_devices(void)
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{
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sysbus_register_withprop(&ioapic_info);
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}
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device_init(ioapic_register_devices)
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4
hw/pc.h
4
hw/pc.h
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@ -39,9 +39,11 @@ void pic_info(Monitor *mon);
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void irq_info(Monitor *mon);
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void irq_info(Monitor *mon);
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/* ISA */
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/* ISA */
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#define IOAPIC_NUM_PINS 0x18
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typedef struct isa_irq_state {
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typedef struct isa_irq_state {
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qemu_irq *i8259;
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qemu_irq *i8259;
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qemu_irq *ioapic;
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qemu_irq ioapic[IOAPIC_NUM_PINS];
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} IsaIrqState;
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} IsaIrqState;
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void isa_irq_handler(void *opaque, int n, int level);
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void isa_irq_handler(void *opaque, int n, int level);
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19
hw/pc_piix.c
19
hw/pc_piix.c
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@ -33,6 +33,7 @@
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#include "ide.h"
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#include "ide.h"
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#include "kvm.h"
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#include "kvm.h"
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#include "sysemu.h"
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#include "sysemu.h"
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#include "sysbus.h"
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#define MAX_IDE_BUS 2
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#define MAX_IDE_BUS 2
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@ -40,6 +41,22 @@ static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 };
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static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
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static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
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static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
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static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
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static void ioapic_init(IsaIrqState *isa_irq_state)
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{
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DeviceState *dev;
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SysBusDevice *d;
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unsigned int i;
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dev = qdev_create(NULL, "ioapic");
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qdev_init_nofail(dev);
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d = sysbus_from_qdev(dev);
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sysbus_mmio_map(d, 0, 0xfec00000);
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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isa_irq_state->ioapic[i] = qdev_get_gpio_in(dev, i);
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}
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}
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/* PC hardware initialisation */
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/* PC hardware initialisation */
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static void pc_init1(ram_addr_t ram_size,
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static void pc_init1(ram_addr_t ram_size,
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const char *boot_device,
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const char *boot_device,
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@ -77,7 +94,7 @@ static void pc_init1(ram_addr_t ram_size,
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isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
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isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
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isa_irq_state->i8259 = i8259;
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isa_irq_state->i8259 = i8259;
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if (pci_enabled) {
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if (pci_enabled) {
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isa_irq_state->ioapic = ioapic_init();
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ioapic_init(isa_irq_state);
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}
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}
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isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
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isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
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