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ppc4xx: Fix code style problems reported by checkpatch

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Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <62798fbe9c200da3e0c870601ed9162b1c3a50a5.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
BALATON Zoltan 2022-08-17 17:08:43 +02:00 • committed by Daniel Henrique Barboza
parent 1b46bc17f4
commit 95e2293287
5 changed files with 67 additions and 47 deletions
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31
hw/ppc/ppc4xx_pci.c
View file

@ -16,8 +16,10 @@
* Authors: Hollis Blanchard <hollisb@us.ibm.com>
*/
/* This file implements emulation of the 32-bit PCI controller found in some
* 4xx SoCs, such as the 440EP. */
/*
* This file implements emulation of the 32-bit PCI controller found in some
* 4xx SoCs, such as the 440EP.
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
@ -65,8 +67,10 @@ struct PPC4xxPCIState {
#define PCIC0_CFGADDR 0x0
#define PCIC0_CFGDATA 0x4
/* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
* PCI accesses. */
/*
* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
* PCI accesses.
*/
#define PCIL0_PMM0LA 0x0
#define PCIL0_PMM0MA 0x4
#define PCIL0_PMM0PCILA 0x8
@ -80,8 +84,10 @@ struct PPC4xxPCIState {
#define PCIL0_PMM2PCILA 0x28
#define PCIL0_PMM2PCIHA 0x2c
/* PCI Target Map (PTM) registers specify which PCI addresses are translated to
* PLB accesses. */
/*
* PCI Target Map (PTM) registers specify which PCI addresses are translated to
* PLB accesses.
*/
#define PCIL0_PTM1MS 0x30
#define PCIL0_PTM1LA 0x34
#define PCIL0_PTM2MS 0x38
@ -96,9 +102,10 @@ static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
{
struct PPC4xxPCIState *pci = opaque;
/* We ignore all target attempts at PCI configuration, effectively
* assuming a bidirectional 1:1 mapping of PLB and PCI space. */
/*
* We ignore all target attempts at PCI configuration, effectively
* assuming a bidirectional 1:1 mapping of PLB and PCI space.
*/
switch (offset) {
case PCIL0_PMM0LA:
pci->pmm[0].la = value;
@ -243,8 +250,10 @@ static void ppc4xx_pci_reset(void *opaque)
memset(pci->ptm, 0, sizeof(pci->ptm));
}
/* On Bamboo, all pins from each slot are tied to a single board IRQ. This
* may need further refactoring for other boards. */
/*
* On Bamboo, all pins from each slot are tied to a single board IRQ.
* This may need further refactoring for other boards.
*/
static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
{
int slot = PCI_SLOT(pci_dev->devfn);