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trivial patches for 2023-11-16

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Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging

trivial patches for 2023-11-16

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# gpg: Signature made Thu 16 Nov 2023 02:39:42 EST
# gpg:                using RSA key 7B73BAD68BE7A2C289314B22701B4F6B1A693E59
# gpg:                issuer "mjt@tls.msk.ru"
# gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [full]
# gpg:                 aka "Michael Tokarev <mjt@corpit.ru>" [full]
# gpg:                 aka "Michael Tokarev <mjt@debian.org>" [full]
# Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D  4324 457C E0A0 8044 65C5
#      Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931  4B22 701B 4F6B 1A69 3E59

* tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu: (27 commits)
  util/range.c: spelling fix: inbetween
  util/filemonitor-inotify.c: spelling fix: kenel
  tests/qtest/ufs-test.c: spelling fix: tranfer
  tests/qtest/migration-test.c: spelling fix: bandwith
  target/riscv/cpu.h: spelling fix: separatly
  include/hw/virtio/vhost.h: spelling fix: sate
  include/hw/hyperv/dynmem-proto.h: spelling fix: nunber, atleast
  include/block/ufs.h: spelling fix: setted
  hw/net/cadence_gem.c: spelling fixes: Octects
  hw/mem/memory-device.c: spelling fix: ontaining
  contrib/vhost-user-gpu/virgl.c: spelling fix: mesage
  migration/rdma.c: spelling fix: asume
  target/hppa: spelling fixes: Indicies, Truely
  target/arm/tcg: spelling fixes: alse, addreses
  docs/system/arm/emulation.rst: spelling fix: Enhacements
  docs/devel/migration.rst: spelling fixes: doen't, diferent, responsability, recomend
  docs/about/deprecated.rst: spelling fix: becase
  gdbstub: spelling fix: respectivelly
  hw/cxl: spelling fixes: limitaions, potentialy, intialized
  linux-user: spelling fixes: othe, necesary
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2023-11-20 05:22:30 -05:00
commit 95e008b9dd
34 changed files with 46 additions and 50 deletions
Download patch file Download diff file Expand all files Collapse all files

2
target/arm/tcg/helper-a64.c
View file

@ -1414,7 +1414,7 @@ void HELPER(setge)(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc)
/*
* Perform part of a memory copy from the guest memory at fromaddr
* and extending for copysize bytes, to the guest memory at
* toaddr. Both addreses are dirty.
* toaddr. Both addresses are dirty.
*
* Returns the number of bytes actually set, which might be less than
* copysize; the caller should loop until the whole copy has been done.

2
target/arm/tcg/hflags.c
View file

@ -327,7 +327,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1);
}
/*
* For unpriv tag-setting accesses we alse need ATA0. Again, in
* For unpriv tag-setting accesses we also need ATA0. Again, in
* contexts where unpriv and normal insns are the same we
* duplicate the ATA bit to save effort for translate-a64.c.
*/

2
target/hppa/cpu.h
View file

@ -56,7 +56,7 @@
1 << MMU_PL2_IDX | 1 << MMU_PL2_P_IDX | \
1 << MMU_USER_IDX | 1 << MMU_USER_P_IDX)
/* Indicies to flush for access_id changes. */
/* Indices to flush for access_id changes. */
#define HPPA_MMU_FLUSH_P_MASK \
(1 << MMU_KERNEL_P_IDX | 1 << MMU_PL1_P_IDX | \
1 << MMU_PL2_P_IDX | 1 << MMU_USER_P_IDX)

2
target/hppa/machine.c
View file

@ -129,7 +129,7 @@ static int tlb_post_load(void *opaque, int version_id)
/*
* Re-create the interval tree from the valid entries.
* Truely invalid entries should have start == end == 0.
* Truly invalid entries should have start == end == 0.
* Otherwise it should be the in-flight tlb_partial entry.
*/
for (uint32_t i = 0; i < ARRAY_SIZE(env->tlb); ++i) {

4
target/riscv/cpu.h
View file

@ -214,13 +214,13 @@ struct CPUArchState {
/*
* When mideleg[i]=0 and mvien[i]=1, sie[i] is no more
* alias of mie[i] and needs to be maintained separatly.
* alias of mie[i] and needs to be maintained separately.
*/
uint64_t sie;
/*
* When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more
* alias of sie[i] (mie[i]) and needs to be maintained separatly.
* alias of sie[i] (mie[i]) and needs to be maintained separately.
*/
uint64_t vsie;