mirror of
https://github.com/Motorhead1991/qemu.git
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target-arm queue:
* Update copyright dates to 2022 * hw/armv7m: Fix broken VMStateDescription * hw/char/exynos4210_uart: Fix crash on trying to load VM state * rtc: Move RTC function prototypes to their own header * xlnx-versal-virt: Support PMC SLCR * xlnx-versal-virt: Support OSPI flash memory controller * scripts: Explain the difference between linux-headers and standard-headers * target/arm: Log CPU index in 'Taking exception' log * arm_gicv3_its: Various bugfixes and cleanups * arm_gicv3_its: Implement the missing MOVI and MOVALL commands * ast2600: Fix address mapping of second SPI controller * target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmH0C+AZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3gG4D/9biXPVdkOd7lIslRX0ihRg AZkZrMNk6VF/MW6xJNVWWd+44cyjLopFqF5dS+Vjebt7pEtZvxY0K5mYmzClk6lg 2U89gWuLEDJDKNVfKAmsmj24Os4xRj4sJPq/Mee8lsBdOAwEQ3C36p0RnWGBcTJN 9VfzRMSGvdjQFJjGAaro078zrA1Q11msA4BbLht+YGTE1aeyryyfF/qGSRlrlTn8 +r0ZWBD4ttz8IsqSLtnpQvT6EbL79w0jBywVauVzCOGQGpti3HdHJNYR7cKgTMja Hffx6f6iv/O4SAUUGS0WMWdfW/MEVxOFxJ7Zc2twGqDMuVWlFiLT0X1MZuHi0FpG CjbhTsvJIrKom1Ib+LPkWscrlHHEf0cvME0WokErLOJDXvbqKj04oOkpQmqUIv0+ 5j7o4mlQFuLXIyzcrBZxmwT/Ekg8KZA8aUR0ddUd0vBmGMdO2En/c4Qr/x4H2gXH HL/18oPRaSV6mP08mxcda+hJ9m5MC+7l0+KKoDfaPM9d4hl5StI0zTlH+5ffbK+m UWthMnrrZw2ZU8AzGPZxOAW5K5S3XOso5Z9credkRGuSDriaGuNY0s5gSvNawZGe ioIrUl50t+5/o2+tba7FA2ePiGeC9/zS671zHG9Rdpe86JpJXCzWO7OYiVulV3Yu dmQYrhgnUqNjh3SAiXUFVA== =m7N5 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220128' into staging target-arm queue: * Update copyright dates to 2022 * hw/armv7m: Fix broken VMStateDescription * hw/char/exynos4210_uart: Fix crash on trying to load VM state * rtc: Move RTC function prototypes to their own header * xlnx-versal-virt: Support PMC SLCR * xlnx-versal-virt: Support OSPI flash memory controller * scripts: Explain the difference between linux-headers and standard-headers * target/arm: Log CPU index in 'Taking exception' log * arm_gicv3_its: Various bugfixes and cleanups * arm_gicv3_its: Implement the missing MOVI and MOVALL commands * ast2600: Fix address mapping of second SPI controller * target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp # gpg: Signature made Fri 28 Jan 2022 15:29:36 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20220128: (32 commits) target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp hw/arm: ast2600: Fix address mapping of second SPI controller hw/intc/arm_gicv3_its: Implement MOVI hw/intc/arm_gicv3_its: Implement MOVALL hw/intc/arm_gicv3_its: Check table bounds against correct limit hw/intc/arm_gicv3_its: Make GITS_BASER<n> RAZ/WI for unimplemented registers hw/intc/arm_gicv3_its: Provide read accessor for translation_ops hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are supported hw/intc/arm_gicv3_redist: Remove unnecessary zero checks hw/intc/arm_gicv3_its: Sort ITS command list into numeric order hw/intc/arm_gicv3: Honour GICD_CTLR.EnableGrp1NS for LPIs hw/intc/arm_gicv3_its: Don't clear GITS_CWRITER on writes to GITS_CBASER hw/intc/arm_gicv3_its: Don't clear GITS_CREADR when GITS_CTLR.ENABLED is set hw/intc/arm_gicv3: Initialise dma_as in GIC, not ITS hw/intc/arm_gicv3_its: Add tracepoints target/arm: Log CPU index in 'Taking exception' log scripts: Explain the difference between linux-headers and standard-headers MAINTAINERS: Remove myself (for raspi). MAINTAINERS: Add an entry for Xilinx Versal OSPI hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
95a6af2a00
52 changed files with 4300 additions and 74 deletions
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@ -26,6 +26,9 @@
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#include "hw/misc/xlnx-versal-xramc.h"
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#include "hw/nvram/xlnx-bbram.h"
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#include "hw/nvram/xlnx-versal-efuse.h"
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#include "hw/ssi/xlnx-versal-ospi.h"
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#include "hw/dma/xlnx_csu_dma.h"
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#include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
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#define TYPE_XLNX_VERSAL "xlnx-versal"
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OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
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@ -78,6 +81,15 @@ struct Versal {
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struct {
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struct {
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SDHCIState sd[XLNX_VERSAL_NR_SDS];
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XlnxVersalPmcIouSlcr slcr;
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struct {
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XlnxVersalOspi ospi;
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XlnxCSUDMA dma_src;
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XlnxCSUDMA dma_dst;
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MemoryRegion linear_mr;
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qemu_or_irq irq_orgate;
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} ospi;
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} iou;
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XlnxZynqMPRTC rtc;
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@ -85,6 +97,8 @@ struct Versal {
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XlnxEFuse efuse;
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XlnxVersalEFuseCtrl efuse_ctrl;
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XlnxVersalEFuseCache efuse_cache;
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qemu_or_irq apb_irq_orgate;
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} pmc;
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struct {
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@ -111,8 +125,8 @@ struct Versal {
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#define VERSAL_GEM1_WAKE_IRQ_0 59
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#define VERSAL_ADMA_IRQ_0 60
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#define VERSAL_XRAM_IRQ_0 79
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#define VERSAL_BBRAM_APB_IRQ_0 121
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#define VERSAL_RTC_APB_ERR_IRQ 121
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#define VERSAL_PMC_APB_IRQ 121
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#define VERSAL_OSPI_IRQ 124
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#define VERSAL_SD0_IRQ_0 126
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#define VERSAL_EFUSE_IRQ 139
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#define VERSAL_RTC_ALARM_IRQ 142
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@ -178,6 +192,18 @@ struct Versal {
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#define MM_FPD_FPD_APU 0xfd5c0000
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#define MM_FPD_FPD_APU_SIZE 0x100
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#define MM_PMC_PMC_IOU_SLCR 0xf1060000
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#define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000
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#define MM_PMC_OSPI 0xf1010000
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#define MM_PMC_OSPI_SIZE 0x10000
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#define MM_PMC_OSPI_DAC 0xc0000000
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#define MM_PMC_OSPI_DAC_SIZE 0x20000000
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#define MM_PMC_OSPI_DMA_DST 0xf1011800
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#define MM_PMC_OSPI_DMA_SRC 0xf1011000
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#define MM_PMC_SD0 0xf1040000U
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#define MM_PMC_SD0_SIZE 0x10000
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#define MM_PMC_BBRAM_CTRL 0xf11f0000
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@ -21,6 +21,11 @@
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#ifndef XLNX_CSU_DMA_H
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#define XLNX_CSU_DMA_H
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#include "hw/sysbus.h"
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#include "hw/register.h"
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#include "hw/ptimer.h"
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#include "hw/stream.h"
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#define TYPE_XLNX_CSU_DMA "xlnx.csu_dma"
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#define XLNX_CSU_DMA_R_MAX (0x2c / 4)
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@ -46,7 +51,22 @@ typedef struct XlnxCSUDMA {
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RegisterInfo regs_info[XLNX_CSU_DMA_R_MAX];
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} XlnxCSUDMA;
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#define XLNX_CSU_DMA(obj) \
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OBJECT_CHECK(XlnxCSUDMA, (obj), TYPE_XLNX_CSU_DMA)
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OBJECT_DECLARE_TYPE(XlnxCSUDMA, XlnxCSUDMAClass, XLNX_CSU_DMA)
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struct XlnxCSUDMAClass {
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SysBusDeviceClass parent_class;
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/*
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* read: Start a read transfer on a Xilinx CSU DMA engine
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*
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* @s: the Xilinx CSU DMA engine to start the transfer on
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* @addr: the address to read
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* @len: the number of bytes to read at 'addr'
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*
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* @return a MemTxResult indicating whether the operation succeeded ('len'
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* bytes were read) or failed.
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*/
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MemTxResult (*read)(XlnxCSUDMA *s, hwaddr addr, uint32_t len);
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};
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#endif
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@ -47,7 +47,6 @@ typedef struct {
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uint16_t entry_sz;
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uint32_t page_sz;
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uint32_t num_entries;
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uint32_t num_ids;
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uint64_t base_addr;
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} TableDesc;
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78
include/hw/misc/xlnx-versal-pmc-iou-slcr.h
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78
include/hw/misc/xlnx-versal-pmc-iou-slcr.h
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@ -0,0 +1,78 @@
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/*
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* Header file for the Xilinx Versal's PMC IOU SLCR
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*
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* Copyright (C) 2021 Xilinx Inc
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* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* This is a model of Xilinx Versal's PMC I/O Peripheral Control and Status
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* module documented in Versal's Technical Reference manual [1] and the Versal
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* ACAP Register reference [2].
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*
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* References:
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*
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* [1] Versal ACAP Technical Reference Manual,
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* https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
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*
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* [2] Versal ACAP Register Reference,
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* https://www.xilinx.com/html_docs/registers/am012/am012-versal-register-reference.html#mod___pmc_iop_slcr.html
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*
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* QEMU interface:
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* + sysbus MMIO region 0: MemoryRegion for the device's registers
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* + sysbus IRQ 0: PMC (AXI and APB) parity error interrupt detected by the PMC
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* I/O peripherals.
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* + sysbus IRQ 1: Device interrupt.
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* + Named GPIO output "sd-emmc-sel[0]": Enables 0: SD mode or 1: eMMC mode on
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* SD/eMMC controller 0.
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* + Named GPIO output "sd-emmc-sel[1]": Enables 0: SD mode or 1: eMMC mode on
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* SD/eMMC controller 1.
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* + Named GPIO output "qspi-ospi-mux-sel": Selects 0: QSPI linear region or 1:
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* OSPI linear region.
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* + Named GPIO output "ospi-mux-sel": Selects 0: OSPI Indirect access mode or
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* 1: OSPI direct access mode.
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*/
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#ifndef XILINX_VERSAL_PMC_IOU_SLCR_H
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#define XILINX_VERSAL_PMC_IOU_SLCR_H
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#include "hw/register.h"
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#define TYPE_XILINX_VERSAL_PMC_IOU_SLCR "xlnx.versal-pmc-iou-slcr"
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalPmcIouSlcr, XILINX_VERSAL_PMC_IOU_SLCR)
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#define XILINX_VERSAL_PMC_IOU_SLCR_R_MAX (0x828 / 4 + 1)
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struct XlnxVersalPmcIouSlcr {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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qemu_irq irq_parity_imr;
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qemu_irq irq_imr;
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qemu_irq sd_emmc_sel[2];
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qemu_irq qspi_ospi_mux_sel;
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qemu_irq ospi_mux_sel;
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uint32_t regs[XILINX_VERSAL_PMC_IOU_SLCR_R_MAX];
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RegisterInfo regs_info[XILINX_VERSAL_PMC_IOU_SLCR_R_MAX];
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};
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#endif /* XILINX_VERSAL_PMC_IOU_SLCR_H */
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111
include/hw/ssi/xlnx-versal-ospi.h
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111
include/hw/ssi/xlnx-versal-ospi.h
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@ -0,0 +1,111 @@
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/*
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* Header file for the Xilinx Versal's OSPI controller
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*
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* Copyright (C) 2021 Xilinx Inc
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* Written by Francisco Iglesias <francisco.iglesias@xilinx.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* This is a model of Xilinx Versal's Octal SPI flash memory controller
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* documented in Versal's Technical Reference manual [1] and the Versal ACAP
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* Register reference [2].
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*
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* References:
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*
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* [1] Versal ACAP Technical Reference Manual,
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* https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
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*
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* [2] Versal ACAP Register Reference,
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* https://www.xilinx.com/html_docs/registers/am012/am012-versal-register-reference.html#mod___ospi.html
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*
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*
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* QEMU interface:
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* + sysbus MMIO region 0: MemoryRegion for the device's registers
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* + sysbus MMIO region 1: MemoryRegion for flash memory linear address space
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* (data transfer).
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* + sysbus IRQ 0: Device interrupt.
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* + Named GPIO input "ospi-mux-sel": 0: enables indirect access mode
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* and 1: enables direct access mode.
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* + Property "dac-with-indac": Allow both direct accesses and indirect
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* accesses simultaneously.
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* + Property "indac-write-disabled": Disable indirect access writes.
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*/
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#ifndef XILINX_VERSAL_OSPI_H
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#define XILINX_VERSAL_OSPI_H
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#include "hw/register.h"
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#include "hw/ssi/ssi.h"
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#include "qemu/fifo8.h"
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#include "hw/dma/xlnx_csu_dma.h"
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#define TYPE_XILINX_VERSAL_OSPI "xlnx.versal-ospi"
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalOspi, XILINX_VERSAL_OSPI)
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#define XILINX_VERSAL_OSPI_R_MAX (0xfc / 4 + 1)
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/*
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* Indirect operations
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*/
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typedef struct IndOp {
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uint32_t flash_addr;
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uint32_t num_bytes;
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uint32_t done_bytes;
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bool completed;
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} IndOp;
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struct XlnxVersalOspi {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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MemoryRegion iomem_dac;
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uint8_t num_cs;
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qemu_irq *cs_lines;
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SSIBus *spi;
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Fifo8 rx_fifo;
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Fifo8 tx_fifo;
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Fifo8 rx_sram;
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Fifo8 tx_sram;
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qemu_irq irq;
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XlnxCSUDMA *dma_src;
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bool ind_write_disabled;
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bool dac_with_indac;
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bool dac_enable;
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bool src_dma_inprog;
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IndOp rd_ind_op[2];
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IndOp wr_ind_op[2];
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uint32_t regs[XILINX_VERSAL_OSPI_R_MAX];
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RegisterInfo regs_info[XILINX_VERSAL_OSPI_R_MAX];
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/* Maximum inferred membank size is 512 bytes */
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uint8_t stig_membank[512];
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};
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#endif /* XILINX_VERSAL_OSPI_H */
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