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target/riscv: vector single-width integer multiply instructions
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200701152549.1218-19-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
LIU Zhiwei
Alistair Francis
parent
558fa7797c
commit
958b85f368
4 changed files with 214 additions and 0 deletions
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@ -859,6 +859,10 @@ GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl)
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#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t
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#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t
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#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t
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#define OP_SUS_B int8_t, uint8_t, int8_t, uint8_t, int8_t
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#define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t
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#define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t
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#define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t
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/* operation of two vector elements */
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typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
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@ -1603,3 +1607,162 @@ GEN_VEXT_VX(vmax_vx_b, 1, 1, clearb)
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GEN_VEXT_VX(vmax_vx_h, 2, 2, clearh)
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GEN_VEXT_VX(vmax_vx_w, 4, 4, clearl)
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GEN_VEXT_VX(vmax_vx_d, 8, 8, clearq)
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/* Vector Single-Width Integer Multiply Instructions */
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#define DO_MUL(N, M) (N * M)
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RVVCALL(OPIVV2, vmul_vv_b, OP_SSS_B, H1, H1, H1, DO_MUL)
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RVVCALL(OPIVV2, vmul_vv_h, OP_SSS_H, H2, H2, H2, DO_MUL)
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RVVCALL(OPIVV2, vmul_vv_w, OP_SSS_W, H4, H4, H4, DO_MUL)
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RVVCALL(OPIVV2, vmul_vv_d, OP_SSS_D, H8, H8, H8, DO_MUL)
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GEN_VEXT_VV(vmul_vv_b, 1, 1, clearb)
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GEN_VEXT_VV(vmul_vv_h, 2, 2, clearh)
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GEN_VEXT_VV(vmul_vv_w, 4, 4, clearl)
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GEN_VEXT_VV(vmul_vv_d, 8, 8, clearq)
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static int8_t do_mulh_b(int8_t s2, int8_t s1)
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{
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return (int16_t)s2 * (int16_t)s1 >> 8;
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}
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static int16_t do_mulh_h(int16_t s2, int16_t s1)
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{
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return (int32_t)s2 * (int32_t)s1 >> 16;
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}
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static int32_t do_mulh_w(int32_t s2, int32_t s1)
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{
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return (int64_t)s2 * (int64_t)s1 >> 32;
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}
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static int64_t do_mulh_d(int64_t s2, int64_t s1)
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{
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uint64_t hi_64, lo_64;
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muls64(&lo_64, &hi_64, s1, s2);
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return hi_64;
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}
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static uint8_t do_mulhu_b(uint8_t s2, uint8_t s1)
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{
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return (uint16_t)s2 * (uint16_t)s1 >> 8;
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}
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static uint16_t do_mulhu_h(uint16_t s2, uint16_t s1)
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{
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return (uint32_t)s2 * (uint32_t)s1 >> 16;
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}
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static uint32_t do_mulhu_w(uint32_t s2, uint32_t s1)
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{
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return (uint64_t)s2 * (uint64_t)s1 >> 32;
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}
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static uint64_t do_mulhu_d(uint64_t s2, uint64_t s1)
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{
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uint64_t hi_64, lo_64;
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mulu64(&lo_64, &hi_64, s2, s1);
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return hi_64;
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}
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static int8_t do_mulhsu_b(int8_t s2, uint8_t s1)
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{
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return (int16_t)s2 * (uint16_t)s1 >> 8;
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}
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static int16_t do_mulhsu_h(int16_t s2, uint16_t s1)
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{
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return (int32_t)s2 * (uint32_t)s1 >> 16;
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}
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static int32_t do_mulhsu_w(int32_t s2, uint32_t s1)
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{
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return (int64_t)s2 * (uint64_t)s1 >> 32;
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}
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/*
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* Let A = signed operand,
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* B = unsigned operand
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* P = mulu64(A, B), unsigned product
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*
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* LET X = 2 ** 64 - A, 2's complement of A
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* SP = signed product
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* THEN
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* IF A < 0
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* SP = -X * B
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* = -(2 ** 64 - A) * B
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* = A * B - 2 ** 64 * B
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* = P - 2 ** 64 * B
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* ELSE
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* SP = P
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* THEN
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* HI_P -= (A < 0 ? B : 0)
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*/
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static int64_t do_mulhsu_d(int64_t s2, uint64_t s1)
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{
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uint64_t hi_64, lo_64;
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mulu64(&lo_64, &hi_64, s2, s1);
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hi_64 -= s2 < 0 ? s1 : 0;
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return hi_64;
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}
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RVVCALL(OPIVV2, vmulh_vv_b, OP_SSS_B, H1, H1, H1, do_mulh_b)
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RVVCALL(OPIVV2, vmulh_vv_h, OP_SSS_H, H2, H2, H2, do_mulh_h)
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RVVCALL(OPIVV2, vmulh_vv_w, OP_SSS_W, H4, H4, H4, do_mulh_w)
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RVVCALL(OPIVV2, vmulh_vv_d, OP_SSS_D, H8, H8, H8, do_mulh_d)
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RVVCALL(OPIVV2, vmulhu_vv_b, OP_UUU_B, H1, H1, H1, do_mulhu_b)
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RVVCALL(OPIVV2, vmulhu_vv_h, OP_UUU_H, H2, H2, H2, do_mulhu_h)
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RVVCALL(OPIVV2, vmulhu_vv_w, OP_UUU_W, H4, H4, H4, do_mulhu_w)
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RVVCALL(OPIVV2, vmulhu_vv_d, OP_UUU_D, H8, H8, H8, do_mulhu_d)
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RVVCALL(OPIVV2, vmulhsu_vv_b, OP_SUS_B, H1, H1, H1, do_mulhsu_b)
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RVVCALL(OPIVV2, vmulhsu_vv_h, OP_SUS_H, H2, H2, H2, do_mulhsu_h)
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RVVCALL(OPIVV2, vmulhsu_vv_w, OP_SUS_W, H4, H4, H4, do_mulhsu_w)
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RVVCALL(OPIVV2, vmulhsu_vv_d, OP_SUS_D, H8, H8, H8, do_mulhsu_d)
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GEN_VEXT_VV(vmulh_vv_b, 1, 1, clearb)
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GEN_VEXT_VV(vmulh_vv_h, 2, 2, clearh)
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GEN_VEXT_VV(vmulh_vv_w, 4, 4, clearl)
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GEN_VEXT_VV(vmulh_vv_d, 8, 8, clearq)
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GEN_VEXT_VV(vmulhu_vv_b, 1, 1, clearb)
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GEN_VEXT_VV(vmulhu_vv_h, 2, 2, clearh)
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GEN_VEXT_VV(vmulhu_vv_w, 4, 4, clearl)
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GEN_VEXT_VV(vmulhu_vv_d, 8, 8, clearq)
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GEN_VEXT_VV(vmulhsu_vv_b, 1, 1, clearb)
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GEN_VEXT_VV(vmulhsu_vv_h, 2, 2, clearh)
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GEN_VEXT_VV(vmulhsu_vv_w, 4, 4, clearl)
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GEN_VEXT_VV(vmulhsu_vv_d, 8, 8, clearq)
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RVVCALL(OPIVX2, vmul_vx_b, OP_SSS_B, H1, H1, DO_MUL)
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RVVCALL(OPIVX2, vmul_vx_h, OP_SSS_H, H2, H2, DO_MUL)
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RVVCALL(OPIVX2, vmul_vx_w, OP_SSS_W, H4, H4, DO_MUL)
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RVVCALL(OPIVX2, vmul_vx_d, OP_SSS_D, H8, H8, DO_MUL)
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RVVCALL(OPIVX2, vmulh_vx_b, OP_SSS_B, H1, H1, do_mulh_b)
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RVVCALL(OPIVX2, vmulh_vx_h, OP_SSS_H, H2, H2, do_mulh_h)
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RVVCALL(OPIVX2, vmulh_vx_w, OP_SSS_W, H4, H4, do_mulh_w)
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RVVCALL(OPIVX2, vmulh_vx_d, OP_SSS_D, H8, H8, do_mulh_d)
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RVVCALL(OPIVX2, vmulhu_vx_b, OP_UUU_B, H1, H1, do_mulhu_b)
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RVVCALL(OPIVX2, vmulhu_vx_h, OP_UUU_H, H2, H2, do_mulhu_h)
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RVVCALL(OPIVX2, vmulhu_vx_w, OP_UUU_W, H4, H4, do_mulhu_w)
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RVVCALL(OPIVX2, vmulhu_vx_d, OP_UUU_D, H8, H8, do_mulhu_d)
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RVVCALL(OPIVX2, vmulhsu_vx_b, OP_SUS_B, H1, H1, do_mulhsu_b)
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RVVCALL(OPIVX2, vmulhsu_vx_h, OP_SUS_H, H2, H2, do_mulhsu_h)
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RVVCALL(OPIVX2, vmulhsu_vx_w, OP_SUS_W, H4, H4, do_mulhsu_w)
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RVVCALL(OPIVX2, vmulhsu_vx_d, OP_SUS_D, H8, H8, do_mulhsu_d)
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GEN_VEXT_VX(vmul_vx_b, 1, 1, clearb)
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GEN_VEXT_VX(vmul_vx_h, 2, 2, clearh)
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GEN_VEXT_VX(vmul_vx_w, 4, 4, clearl)
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GEN_VEXT_VX(vmul_vx_d, 8, 8, clearq)
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GEN_VEXT_VX(vmulh_vx_b, 1, 1, clearb)
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GEN_VEXT_VX(vmulh_vx_h, 2, 2, clearh)
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GEN_VEXT_VX(vmulh_vx_w, 4, 4, clearl)
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GEN_VEXT_VX(vmulh_vx_d, 8, 8, clearq)
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GEN_VEXT_VX(vmulhu_vx_b, 1, 1, clearb)
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GEN_VEXT_VX(vmulhu_vx_h, 2, 2, clearh)
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GEN_VEXT_VX(vmulhu_vx_w, 4, 4, clearl)
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GEN_VEXT_VX(vmulhu_vx_d, 8, 8, clearq)
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GEN_VEXT_VX(vmulhsu_vx_b, 1, 1, clearb)
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GEN_VEXT_VX(vmulhsu_vx_h, 2, 2, clearh)
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GEN_VEXT_VX(vmulhsu_vx_w, 4, 4, clearl)
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GEN_VEXT_VX(vmulhsu_vx_d, 8, 8, clearq)
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