mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-05 16:53:55 -06:00
Third RISC-V PR for 8.1
* Use xl instead of mxl for disassemble * Factor out extension tests to cpu_cfg.h * disas/riscv: Add vendor extension support * disas/riscv: Add support for XVentanaCondOps * disas/riscv: Add support for XThead* instructions * Fix mstatus related problems * Fix veyron-v1 CPU properties * Fix the xlen for data address when MPRV=1 * opensbi: Upgrade from v1.2 to v1.3 * Enable 32-bit Spike OpenSBI boot testing * Support the watchdog timer of HiFive 1 rev b * Only build qemu-system-riscv$$ on rv$$ host * Add RVV registers to log * Restrict ACLINT to TCG * Add syscall riscv_hwprobe * Add support for BF16 extensions * KVM_RISCV_SET_TIMER macro is not configured correctly * Generate devicetree only after machine initialization is complete * virt: Convert fdt_load_addr to uint64_t * KVM: fixes and enhancements * Add support for the Zfa extension -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmSr+ekACgkQr3yVEwxT gBMMGg//ZCcyH3KXB49c2KUIFO6FKYUxN9uC3giZCtuGyEH8T2yDgZVVXnxwU+Ij +3Ej6T/ZdWMpePC9qf+xKzHWZk7Qc8Tcg+JgQbga573894yZInRwYl8HsSlEKA+Z vlqSBPxTlp9rlDwGP/LjGljyIFqL4konk9zi3FL4ZXTF1iHUGrh/953Y3wIreEfl KX5UznnWcgy2BqQT1vihMbM8qCVK6iryH+QZ6LiAsPMSX1rIzk8ectQryILzoIYh bMiwCLVMyr4ZrUXjmGTF+7/WcOWwhhyfpdstf2iotKALelZtVHit0wHcty2GYQde nvN83jJWu04DGXkPBUsqCUQXczGo1QHjJUH3RIRJzfOby/lGt4pSzHAfKA+iNUht ikM3SdBsXMO+ogjTtTcCMb7/m2vsMoQP60VRts9Mh3YVD0cgr7RqpqRoEMugVYnr ca8Vijf71mB+y+pq477eV1Q8BoKpr8xa1OlFkNKPC17uMD7HoDMI44QgFOgtYp10 TMsqqyB75q6PZhSEwm63xbmH0Zpo8kSqT/E3MTtGTyPeuL8TNNNSkCmFaGYmRrbI XEp7vG2RaDJOvDomS3nUhA5ruc8SaXd0q25q2gLYQfCsehfFqZAwuNB5xf1zS0M0 ov1/gwaqU93t6nLbo2cCbb0plkIFKwwJ9KKjD06wJ4KPe0TGFzk= =3XFD -----END PGP SIGNATURE----- Merge tag 'pull-riscv-to-apply-20230710-1' of https://github.com/alistair23/qemu into staging Third RISC-V PR for 8.1 * Use xl instead of mxl for disassemble * Factor out extension tests to cpu_cfg.h * disas/riscv: Add vendor extension support * disas/riscv: Add support for XVentanaCondOps * disas/riscv: Add support for XThead* instructions * Fix mstatus related problems * Fix veyron-v1 CPU properties * Fix the xlen for data address when MPRV=1 * opensbi: Upgrade from v1.2 to v1.3 * Enable 32-bit Spike OpenSBI boot testing * Support the watchdog timer of HiFive 1 rev b * Only build qemu-system-riscv$$ on rv$$ host * Add RVV registers to log * Restrict ACLINT to TCG * Add syscall riscv_hwprobe * Add support for BF16 extensions * KVM_RISCV_SET_TIMER macro is not configured correctly * Generate devicetree only after machine initialization is complete * virt: Convert fdt_load_addr to uint64_t * KVM: fixes and enhancements * Add support for the Zfa extension # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmSr+ekACgkQr3yVEwxT # gBMMGg//ZCcyH3KXB49c2KUIFO6FKYUxN9uC3giZCtuGyEH8T2yDgZVVXnxwU+Ij # +3Ej6T/ZdWMpePC9qf+xKzHWZk7Qc8Tcg+JgQbga573894yZInRwYl8HsSlEKA+Z # vlqSBPxTlp9rlDwGP/LjGljyIFqL4konk9zi3FL4ZXTF1iHUGrh/953Y3wIreEfl # KX5UznnWcgy2BqQT1vihMbM8qCVK6iryH+QZ6LiAsPMSX1rIzk8ectQryILzoIYh # bMiwCLVMyr4ZrUXjmGTF+7/WcOWwhhyfpdstf2iotKALelZtVHit0wHcty2GYQde # nvN83jJWu04DGXkPBUsqCUQXczGo1QHjJUH3RIRJzfOby/lGt4pSzHAfKA+iNUht # ikM3SdBsXMO+ogjTtTcCMb7/m2vsMoQP60VRts9Mh3YVD0cgr7RqpqRoEMugVYnr # ca8Vijf71mB+y+pq477eV1Q8BoKpr8xa1OlFkNKPC17uMD7HoDMI44QgFOgtYp10 # TMsqqyB75q6PZhSEwm63xbmH0Zpo8kSqT/E3MTtGTyPeuL8TNNNSkCmFaGYmRrbI # XEp7vG2RaDJOvDomS3nUhA5ruc8SaXd0q25q2gLYQfCsehfFqZAwuNB5xf1zS0M0 # ov1/gwaqU93t6nLbo2cCbb0plkIFKwwJ9KKjD06wJ4KPe0TGFzk= # =3XFD # -----END PGP SIGNATURE----- # gpg: Signature made Mon 10 Jul 2023 01:30:33 PM BST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20230710-1' of https://github.com/alistair23/qemu: (54 commits) riscv: Add support for the Zfa extension target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper target/riscv: update multi-letter extension KVM properties target/riscv/cpu.c: create KVM mock properties target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext() target/riscv/cpu.c: add satp_mode properties earlier target/riscv/kvm.c: add multi-letter extension KVM properties target/riscv/kvm.c: update KVM MISA bits target/riscv: add KVM specific MISA properties target/riscv/cpu: add misa_ext_info_arr[] target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids() target/riscv: use KVM scratch CPUs to init KVM properties target/riscv/cpu.c: restrict 'marchid' value target/riscv/cpu.c: restrict 'mimpid' value target/riscv/cpu.c: restrict 'mvendorid' value hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set target/riscv: skip features setup for KVM CPUs ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
commit
94d68c1136
44 changed files with 4751 additions and 442 deletions
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@ -6,7 +6,6 @@
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# later. See the COPYING file in the top-level directory.
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from avocado_qemu import QemuSystemTest
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from avocado import skip
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from avocado_qemu import wait_for_console_pattern
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class RiscvOpenSBI(QemuSystemTest):
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@ -21,7 +20,6 @@ class RiscvOpenSBI(QemuSystemTest):
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wait_for_console_pattern(self, 'Platform Name')
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wait_for_console_pattern(self, 'Boot HART MEDELEG')
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@skip("requires OpenSBI fix to work")
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def test_riscv32_spike(self):
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"""
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:avocado: tags=arch:riscv32
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@ -234,6 +234,9 @@ qtests_s390x = \
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'cpu-plug-test',
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'migration-test']
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qtests_riscv32 = \
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(config_all_devices.has_key('CONFIG_SIFIVE_E_AON') ? ['sifive-e-aon-watchdog-test'] : [])
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qos_test_ss = ss.source_set()
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qos_test_ss.add(
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'ac97-test.c',
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450
tests/qtest/sifive-e-aon-watchdog-test.c
Normal file
450
tests/qtest/sifive-e-aon-watchdog-test.c
Normal file
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@ -0,0 +1,450 @@
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/*
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* QTest testcase for the watchdog timer of HiFive 1 rev b.
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*
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* Copyright (c) 2023 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/timer.h"
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#include "qemu/bitops.h"
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#include "libqtest.h"
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#include "hw/registerfields.h"
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#include "hw/misc/sifive_e_aon.h"
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FIELD(AON_WDT_WDOGCFG, SCALE, 0, 4)
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FIELD(AON_WDT_WDOGCFG, RSVD0, 4, 4)
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FIELD(AON_WDT_WDOGCFG, RSTEN, 8, 1)
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FIELD(AON_WDT_WDOGCFG, ZEROCMP, 9, 1)
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FIELD(AON_WDT_WDOGCFG, RSVD1, 10, 2)
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FIELD(AON_WDT_WDOGCFG, EN_ALWAYS, 12, 1)
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FIELD(AON_WDT_WDOGCFG, EN_CORE_AWAKE, 13, 1)
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FIELD(AON_WDT_WDOGCFG, RSVD2, 14, 14)
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FIELD(AON_WDT_WDOGCFG, IP0, 28, 1)
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FIELD(AON_WDT_WDOGCFG, RSVD3, 29, 3)
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#define WDOG_BASE (0x10000000)
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#define WDOGCFG (0x0)
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#define WDOGCOUNT (0x8)
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#define WDOGS (0x10)
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#define WDOGFEED (0x18)
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#define WDOGKEY (0x1c)
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#define WDOGCMP0 (0x20)
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#define SIFIVE_E_AON_WDOGKEY (0x51F15E)
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#define SIFIVE_E_AON_WDOGFEED (0xD09F00D)
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#define SIFIVE_E_LFCLK_DEFAULT_FREQ (32768)
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static void test_init(QTestState *qts)
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{
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qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
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qtest_writel(qts, WDOG_BASE + WDOGCOUNT, 0);
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qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
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qtest_writel(qts, WDOG_BASE + WDOGCFG, 0);
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qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
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qtest_writel(qts, WDOG_BASE + WDOGCMP0, 0xBEEF);
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}
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static void test_wdogcount(void)
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{
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uint64_t tmp;
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QTestState *qts = qtest_init("-machine sifive_e");
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test_init(qts);
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tmp = qtest_readl(qts, WDOG_BASE + WDOGCOUNT);
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qtest_writel(qts, WDOG_BASE + WDOGCOUNT, 0xBEEF);
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g_assert(qtest_readl(qts, WDOG_BASE + WDOGCOUNT) == tmp);
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qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
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qtest_writel(qts, WDOG_BASE + WDOGCOUNT, 0xBEEF);
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g_assert(0xBEEF == qtest_readl(qts, WDOG_BASE + WDOGCOUNT));
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qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
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qtest_writel(qts, WDOG_BASE + WDOGCOUNT, 0xAAAAAAAA);
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g_assert(0x2AAAAAAA == qtest_readl(qts, WDOG_BASE + WDOGCOUNT));
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qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
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qtest_writel(qts, WDOG_BASE + WDOGFEED, 0xAAAAAAAA);
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g_assert(0x2AAAAAAA == qtest_readl(qts, WDOG_BASE + WDOGCOUNT));
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qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
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qtest_writel(qts, WDOG_BASE + WDOGFEED, SIFIVE_E_AON_WDOGFEED);
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g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGCOUNT));
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qtest_quit(qts);
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}
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static void test_wdogcfg(void)
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{
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uint32_t tmp_cfg;
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QTestState *qts = qtest_init("-machine sifive_e");
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test_init(qts);
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tmp_cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
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qtest_writel(qts, WDOG_BASE + WDOGCFG, 0xFFFFFFFF);
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g_assert(qtest_readl(qts, WDOG_BASE + WDOGCFG) == tmp_cfg);
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qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
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qtest_writel(qts, WDOG_BASE + WDOGCFG, 0xFFFFFFFF);
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g_assert(0xFFFFFFFF == qtest_readl(qts, WDOG_BASE + WDOGCFG));
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tmp_cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
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g_assert(15 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, SCALE));
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g_assert(1 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, RSTEN));
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g_assert(1 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, ZEROCMP));
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g_assert(1 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, EN_ALWAYS));
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g_assert(1 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE));
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g_assert(1 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, IP0));
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qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
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qtest_writel(qts, WDOG_BASE + WDOGCFG, 0);
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tmp_cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
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g_assert(0 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, SCALE));
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g_assert(0 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, RSTEN));
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g_assert(0 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, ZEROCMP));
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g_assert(0 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, EN_ALWAYS));
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g_assert(0 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE));
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g_assert(0 == FIELD_EX32(tmp_cfg, AON_WDT_WDOGCFG, IP0));
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g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGCFG));
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qtest_quit(qts);
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}
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static void test_wdogcmp0(void)
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{
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uint32_t tmp;
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QTestState *qts = qtest_init("-machine sifive_e");
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test_init(qts);
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tmp = qtest_readl(qts, WDOG_BASE + WDOGCMP0);
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qtest_writel(qts, WDOG_BASE + WDOGCMP0, 0xBEEF);
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g_assert(qtest_readl(qts, WDOG_BASE + WDOGCMP0) == tmp);
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qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
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qtest_writel(qts, WDOG_BASE + WDOGCMP0, 0xBEEF);
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g_assert(0xBEEF == qtest_readl(qts, WDOG_BASE + WDOGCMP0));
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qtest_quit(qts);
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}
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static void test_wdogkey(void)
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{
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QTestState *qts = qtest_init("-machine sifive_e");
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test_init(qts);
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g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGKEY));
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qtest_writel(qts, WDOG_BASE + WDOGKEY, 0xFFFF);
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g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGKEY));
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qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
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g_assert(1 == qtest_readl(qts, WDOG_BASE + WDOGKEY));
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qtest_writel(qts, WDOG_BASE + WDOGFEED, 0xAAAAAAAA);
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g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGKEY));
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qtest_quit(qts);
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}
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static void test_wdogfeed(void)
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{
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QTestState *qts = qtest_init("-machine sifive_e");
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test_init(qts);
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g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGFEED));
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qtest_writel(qts, WDOG_BASE + WDOGFEED, 0xFFFF);
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g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGFEED));
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qtest_quit(qts);
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}
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static void test_scaled_wdogs(void)
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{
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uint32_t cfg;
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uint32_t fake_count = 0x12345678;
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QTestState *qts = qtest_init("-machine sifive_e");
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test_init(qts);
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qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
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qtest_writel(qts, WDOG_BASE + WDOGCOUNT, fake_count);
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g_assert(qtest_readl(qts, WDOG_BASE + WDOGCOUNT) == fake_count);
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g_assert((uint16_t)qtest_readl(qts, WDOG_BASE + WDOGS) ==
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(uint16_t)fake_count);
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for (int i = 0; i < 16; i++) {
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cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
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cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, SCALE, i);
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qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
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qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg);
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g_assert((uint16_t)qtest_readl(qts, WDOG_BASE + WDOGS) ==
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(uint16_t)(fake_count >>
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FIELD_EX32(cfg, AON_WDT_WDOGCFG, SCALE)));
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}
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qtest_quit(qts);
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}
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static void test_watchdog(void)
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{
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uint32_t cfg;
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QTestState *qts = qtest_init("-machine sifive_e");
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test_init(qts);
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qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
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qtest_writel(qts, WDOG_BASE + WDOGCMP0, SIFIVE_E_LFCLK_DEFAULT_FREQ);
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cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
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cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, SCALE, 0);
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cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS, 1);
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qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
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qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg);
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qtest_clock_step(qts, NANOSECONDS_PER_SECOND);
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g_assert(qtest_readl(qts, WDOG_BASE + WDOGCOUNT) ==
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SIFIVE_E_LFCLK_DEFAULT_FREQ);
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g_assert(qtest_readl(qts, WDOG_BASE + WDOGS) ==
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SIFIVE_E_LFCLK_DEFAULT_FREQ);
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cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
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||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, SCALE));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, RSTEN));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, ZEROCMP));
|
||||
g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE));
|
||||
g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0));
|
||||
|
||||
qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGCOUNT, 0);
|
||||
cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, IP0, 0);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg);
|
||||
cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0));
|
||||
|
||||
qtest_quit(qts);
|
||||
}
|
||||
|
||||
static void test_scaled_watchdog(void)
|
||||
{
|
||||
uint32_t cfg;
|
||||
QTestState *qts = qtest_init("-machine sifive_e");
|
||||
|
||||
test_init(qts);
|
||||
|
||||
qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGCMP0, 10);
|
||||
|
||||
cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
|
||||
cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, SCALE, 15);
|
||||
cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS, 1);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg);
|
||||
|
||||
qtest_clock_step(qts, NANOSECONDS_PER_SECOND * 10);
|
||||
|
||||
g_assert(qtest_readl(qts, WDOG_BASE + WDOGCOUNT) ==
|
||||
SIFIVE_E_LFCLK_DEFAULT_FREQ * 10);
|
||||
|
||||
g_assert(10 == qtest_readl(qts, WDOG_BASE + WDOGS));
|
||||
|
||||
cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
|
||||
g_assert(15 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, SCALE));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, RSTEN));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, ZEROCMP));
|
||||
g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE));
|
||||
g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0));
|
||||
|
||||
qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGCOUNT, 0);
|
||||
cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, IP0, 0);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg);
|
||||
cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0));
|
||||
|
||||
qtest_quit(qts);
|
||||
}
|
||||
|
||||
static void test_periodic_int(void)
|
||||
{
|
||||
uint32_t cfg;
|
||||
QTestState *qts = qtest_init("-machine sifive_e");
|
||||
|
||||
test_init(qts);
|
||||
|
||||
qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGCMP0, SIFIVE_E_LFCLK_DEFAULT_FREQ);
|
||||
|
||||
cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
|
||||
cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, SCALE, 0);
|
||||
cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, ZEROCMP, 1);
|
||||
cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS, 1);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg);
|
||||
|
||||
qtest_clock_step(qts, NANOSECONDS_PER_SECOND);
|
||||
|
||||
g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGCOUNT));
|
||||
g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGS));
|
||||
|
||||
cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, SCALE));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, RSTEN));
|
||||
g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, ZEROCMP));
|
||||
g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE));
|
||||
g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0));
|
||||
|
||||
cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, IP0, 0);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg);
|
||||
cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0));
|
||||
|
||||
qtest_clock_step(qts, NANOSECONDS_PER_SECOND);
|
||||
|
||||
g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGCOUNT));
|
||||
g_assert(0 == qtest_readl(qts, WDOG_BASE + WDOGS));
|
||||
|
||||
cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, SCALE));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, RSTEN));
|
||||
g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, ZEROCMP));
|
||||
g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE));
|
||||
g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0));
|
||||
|
||||
cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, IP0, 0);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg);
|
||||
cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0));
|
||||
|
||||
qtest_quit(qts);
|
||||
}
|
||||
|
||||
static void test_enable_disable(void)
|
||||
{
|
||||
uint32_t cfg;
|
||||
QTestState *qts = qtest_init("-machine sifive_e");
|
||||
|
||||
test_init(qts);
|
||||
|
||||
qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGCMP0, 10);
|
||||
|
||||
cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
|
||||
cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, SCALE, 15);
|
||||
cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS, 1);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg);
|
||||
|
||||
qtest_clock_step(qts, NANOSECONDS_PER_SECOND * 2);
|
||||
|
||||
g_assert(qtest_readl(qts, WDOG_BASE + WDOGCOUNT) ==
|
||||
SIFIVE_E_LFCLK_DEFAULT_FREQ * 2);
|
||||
g_assert(2 == qtest_readl(qts, WDOG_BASE + WDOGS));
|
||||
|
||||
cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
|
||||
g_assert(15 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, SCALE));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, RSTEN));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, ZEROCMP));
|
||||
g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0));
|
||||
|
||||
qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
|
||||
cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS, 0);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg);
|
||||
|
||||
qtest_clock_step(qts, NANOSECONDS_PER_SECOND * 8);
|
||||
|
||||
g_assert(qtest_readl(qts, WDOG_BASE + WDOGCOUNT) ==
|
||||
SIFIVE_E_LFCLK_DEFAULT_FREQ * 2);
|
||||
g_assert(2 == qtest_readl(qts, WDOG_BASE + WDOGS));
|
||||
|
||||
cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
|
||||
g_assert(15 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, SCALE));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, RSTEN));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, ZEROCMP));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0));
|
||||
|
||||
cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS, 1);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg);
|
||||
|
||||
qtest_clock_step(qts, NANOSECONDS_PER_SECOND * 8);
|
||||
|
||||
g_assert(qtest_readl(qts, WDOG_BASE + WDOGCOUNT) ==
|
||||
SIFIVE_E_LFCLK_DEFAULT_FREQ * 10);
|
||||
g_assert(10 == qtest_readl(qts, WDOG_BASE + WDOGS));
|
||||
|
||||
cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
|
||||
g_assert(15 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, SCALE));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, RSTEN));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, ZEROCMP));
|
||||
g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_ALWAYS));
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, EN_CORE_AWAKE));
|
||||
g_assert(1 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0));
|
||||
|
||||
qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGCOUNT, 0);
|
||||
cfg = FIELD_DP32(cfg, AON_WDT_WDOGCFG, IP0, 0);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGKEY, SIFIVE_E_AON_WDOGKEY);
|
||||
qtest_writel(qts, WDOG_BASE + WDOGCFG, cfg);
|
||||
cfg = qtest_readl(qts, WDOG_BASE + WDOGCFG);
|
||||
g_assert(0 == FIELD_EX32(cfg, AON_WDT_WDOGCFG, IP0));
|
||||
|
||||
qtest_quit(qts);
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
g_test_init(&argc, &argv, NULL);
|
||||
qtest_add_func("/sifive-e-aon-watchdog-test/wdogcount",
|
||||
test_wdogcount);
|
||||
qtest_add_func("/sifive-e-aon-watchdog-test/wdogcfg",
|
||||
test_wdogcfg);
|
||||
qtest_add_func("/sifive-e-aon-watchdog-test/wdogcmp0",
|
||||
test_wdogcmp0);
|
||||
qtest_add_func("/sifive-e-aon-watchdog-test/wdogkey",
|
||||
test_wdogkey);
|
||||
qtest_add_func("/sifive-e-aon-watchdog-test/wdogfeed",
|
||||
test_wdogfeed);
|
||||
qtest_add_func("/sifive-e-aon-watchdog-test/scaled_wdogs",
|
||||
test_scaled_wdogs);
|
||||
qtest_add_func("/sifive-e-aon-watchdog-test/watchdog",
|
||||
test_watchdog);
|
||||
qtest_add_func("/sifive-e-aon-watchdog-test/scaled_watchdog",
|
||||
test_scaled_watchdog);
|
||||
qtest_add_func("/sifive-e-aon-watchdog-test/periodic_int",
|
||||
test_periodic_int);
|
||||
qtest_add_func("/sifive-e-aon-watchdog-test/enable_disable",
|
||||
test_enable_disable);
|
||||
return g_test_run();
|
||||
}
|
||||
|
|
@ -12,3 +12,9 @@ run-test-noc: QEMU_OPTS += -cpu rv64,c=false
|
|||
|
||||
TESTS += test-aes
|
||||
run-test-aes: QEMU_OPTS += -cpu rv64,zk=on
|
||||
|
||||
# Test for fcvtmod
|
||||
TESTS += test-fcvtmod
|
||||
test-fcvtmod: CFLAGS += -march=rv64imafdc
|
||||
test-fcvtmod: LDFLAGS += -static
|
||||
run-test-fcvtmod: QEMU_OPTS += -cpu rv64,d=true,Zfa=true
|
||||
|
|
|
|||
345
tests/tcg/riscv64/test-fcvtmod.c
Normal file
345
tests/tcg/riscv64/test-fcvtmod.c
Normal file
|
|
@ -0,0 +1,345 @@
|
|||
#include <stdio.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#define FFLAG_NX_SHIFT 0 /* inexact */
|
||||
#define FFLAG_UF_SHIFT 1 /* underflow */
|
||||
#define FFLAG_OF_SHIFT 2 /* overflow */
|
||||
#define FFLAG_DZ_SHIFT 3 /* divide by zero */
|
||||
#define FFLAG_NV_SHIFT 4 /* invalid operation */
|
||||
|
||||
#define FFLAG_NV (1UL << FFLAG_NV_SHIFT)
|
||||
#define FFLAG_DZ (1UL << FFLAG_DZ_SHIFT)
|
||||
#define FFLAG_OF (1UL << FFLAG_OF_SHIFT)
|
||||
#define FFLAG_UF (1UL << FFLAG_UF_SHIFT)
|
||||
#define FFLAG_NX (1UL << FFLAG_NX_SHIFT)
|
||||
|
||||
typedef struct fp64_fcvt_fcvtmod_testcase {
|
||||
const char* name;
|
||||
union {
|
||||
uint64_t inp_lu;
|
||||
double inp_lf;
|
||||
};
|
||||
uint64_t exp_fcvt;
|
||||
uint8_t exp_fcvt_fflags;
|
||||
uint64_t exp_fcvtmod;
|
||||
uint8_t exp_fcvtmod_fflags;
|
||||
} fp64_fcvt_fcvtmod_testcase_t;
|
||||
|
||||
void print_fflags(uint8_t fflags)
|
||||
{
|
||||
int set = 0;
|
||||
|
||||
if (fflags == 0) {
|
||||
printf("-");
|
||||
return;
|
||||
}
|
||||
|
||||
if (fflags & FFLAG_NV) {
|
||||
printf("%sFFLAG_NV", set ? " | " : "");
|
||||
set = 1;
|
||||
}
|
||||
if (fflags & FFLAG_DZ) {
|
||||
printf("%sFFLAG_DZ", set ? " | " : "");
|
||||
set = 1;
|
||||
}
|
||||
if (fflags & FFLAG_OF) {
|
||||
printf("%sFFLAG_OF", set ? " | " : "");
|
||||
set = 1;
|
||||
}
|
||||
if (fflags & FFLAG_UF) {
|
||||
printf("%sFFLAG_UF", set ? " | " : "");
|
||||
set = 1;
|
||||
}
|
||||
if (fflags & FFLAG_NX) {
|
||||
printf("%sFFLAG_NX", set ? " | " : "");
|
||||
set = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear all FP flags. */
|
||||
static inline void clear_fflags()
|
||||
{
|
||||
__asm__ __volatile__("fsflags zero");
|
||||
}
|
||||
|
||||
/* Read all FP flags. */
|
||||
static inline uint8_t get_fflags()
|
||||
{
|
||||
uint64_t v;
|
||||
__asm__ __volatile__("frflags %0" : "=r"(v));
|
||||
return (uint8_t)v;
|
||||
}
|
||||
|
||||
/* Move input value (without conversations) into an FP register. */
|
||||
static inline double do_fmv_d_x(uint64_t inp)
|
||||
{
|
||||
double fpr;
|
||||
__asm__ __volatile__("fmv.d.x %0, %1" : "=f"(fpr) : "r"(inp));
|
||||
return fpr;
|
||||
}
|
||||
|
||||
static inline uint64_t do_fcvt_w_d(uint64_t inp, uint8_t *fflags)
|
||||
{
|
||||
uint64_t ret;
|
||||
double fpr = do_fmv_d_x(inp);
|
||||
|
||||
clear_fflags();
|
||||
|
||||
__asm__ __volatile__("fcvt.w.d %0, %1, rtz" : "=r"(ret) : "f"(fpr));
|
||||
|
||||
*fflags = get_fflags();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline uint64_t do_fcvtmod_w_d(uint64_t inp, uint8_t *fflags)
|
||||
{
|
||||
uint64_t ret;
|
||||
double fpr = do_fmv_d_x(inp);
|
||||
|
||||
clear_fflags();
|
||||
|
||||
/* fcvtmod.w.d rd, rs1, rtz = 1100001 01000 rs1 001 rd 1010011 */
|
||||
asm(".insn r 0x53, 0x1, 0x61, %0, %1, f8" : "=r"(ret) : "f"(fpr));
|
||||
|
||||
*fflags = get_fflags();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const fp64_fcvt_fcvtmod_testcase_t tests[] = {
|
||||
/* Zero (exp=0, frac=0) */
|
||||
{ .name = "+0.0",
|
||||
.inp_lf = 0x0p0,
|
||||
.exp_fcvt = 0x0000000000000000,
|
||||
.exp_fcvt_fflags = 0,
|
||||
.exp_fcvtmod = 0x0000000000000000,
|
||||
.exp_fcvtmod_fflags = 0 },
|
||||
{ .name = "-0.0",
|
||||
.inp_lf = -0x0p0,
|
||||
.exp_fcvt = 0x0000000000000000,
|
||||
.exp_fcvt_fflags = 0,
|
||||
.exp_fcvtmod = 0x0000000000000000,
|
||||
.exp_fcvtmod_fflags = 0 },
|
||||
|
||||
/* Subnormal: exp=0 frac!=0 */
|
||||
{ .name = "Subnormal frac=1",
|
||||
.inp_lu = 0x0000000000000001,
|
||||
.exp_fcvt = 0x0000000000000000,
|
||||
.exp_fcvt_fflags = FFLAG_NX,
|
||||
.exp_fcvtmod = 0,
|
||||
.exp_fcvtmod_fflags = FFLAG_NX },
|
||||
{ .name = "Subnormal frac=0xf..f",
|
||||
.inp_lu = 0x0000ffffffffffff,
|
||||
.exp_fcvt = 0x0000000000000000,
|
||||
.exp_fcvt_fflags = FFLAG_NX,
|
||||
.exp_fcvtmod = 0,
|
||||
.exp_fcvtmod_fflags = FFLAG_NX },
|
||||
{ .name = "Neg subnormal frac=1",
|
||||
.inp_lu = 0x0000000000000001,
|
||||
.exp_fcvt = 0x0000000000000000,
|
||||
.exp_fcvt_fflags = FFLAG_NX,
|
||||
.exp_fcvtmod = 0,
|
||||
.exp_fcvtmod_fflags = FFLAG_NX },
|
||||
{ .name = "Neg subnormal frac=0xf..f",
|
||||
.inp_lu = 0x8000ffffffffffff,
|
||||
.exp_fcvt = 0x0000000000000000,
|
||||
.exp_fcvt_fflags = FFLAG_NX,
|
||||
.exp_fcvtmod = 0,
|
||||
.exp_fcvtmod_fflags = FFLAG_NX },
|
||||
|
||||
/* Infinity: exp=0x7ff, frac=0 */
|
||||
{ .name = "+INF",
|
||||
.inp_lu = 0x7ff0000000000000,
|
||||
.exp_fcvt = 0x000000007fffffff, /* int32 max */
|
||||
.exp_fcvt_fflags = FFLAG_NV,
|
||||
.exp_fcvtmod = 0,
|
||||
.exp_fcvtmod_fflags = FFLAG_NV },
|
||||
{ .name = "-INF",
|
||||
.inp_lu = 0xfff0000000000000,
|
||||
.exp_fcvt = 0xffffffff80000000, /* int32 min */
|
||||
.exp_fcvt_fflags = FFLAG_NV,
|
||||
.exp_fcvtmod = 0,
|
||||
.exp_fcvtmod_fflags = FFLAG_NV },
|
||||
|
||||
/* NaN: exp=7ff, frac!=0 */
|
||||
{ .name = "canonical NaN",
|
||||
.inp_lu = 0x7ff8000000000000,
|
||||
.exp_fcvt = 0x000000007fffffff, /* int32 max */
|
||||
.exp_fcvt_fflags = FFLAG_NV,
|
||||
.exp_fcvtmod = 0,
|
||||
.exp_fcvtmod_fflags = FFLAG_NV },
|
||||
{ .name = "non-canonical NaN",
|
||||
.inp_lu = 0x7ff8000000100000,
|
||||
.exp_fcvt = 0x000000007fffffff, /* int32 min */
|
||||
.exp_fcvt_fflags = FFLAG_NV,
|
||||
.exp_fcvtmod = 0,
|
||||
.exp_fcvtmod_fflags = FFLAG_NV },
|
||||
|
||||
/* Normal numbers: exp!=0, exp!=7ff */
|
||||
{ .name = "+smallest normal value",
|
||||
.inp_lu = 0x0010000000000000,
|
||||
.exp_fcvt = 0,
|
||||
.exp_fcvt_fflags = FFLAG_NX,
|
||||
.exp_fcvtmod = 0,
|
||||
.exp_fcvtmod_fflags = FFLAG_NX },
|
||||
{ .name = "-smallest normal value",
|
||||
.inp_lu = 0x8010000000000000,
|
||||
.exp_fcvt = 0,
|
||||
.exp_fcvt_fflags = FFLAG_NX,
|
||||
.exp_fcvtmod = 0,
|
||||
.exp_fcvtmod_fflags = FFLAG_NX },
|
||||
|
||||
{ .name = "+0.5",
|
||||
.inp_lf = 0x1p-1,
|
||||
.exp_fcvt = 0,
|
||||
.exp_fcvt_fflags = FFLAG_NX,
|
||||
.exp_fcvtmod = 0,
|
||||
.exp_fcvtmod_fflags = FFLAG_NX },
|
||||
{ .name = "-0.5",
|
||||
.inp_lf = -0x1p-1,
|
||||
.exp_fcvt = 0,
|
||||
.exp_fcvt_fflags = FFLAG_NX,
|
||||
.exp_fcvtmod = 0,
|
||||
.exp_fcvtmod_fflags = FFLAG_NX },
|
||||
|
||||
{ .name = "+value just below 1.0",
|
||||
.inp_lu = 0x3fefffffffffffff,
|
||||
.exp_fcvt = 0,
|
||||
.exp_fcvt_fflags = FFLAG_NX,
|
||||
.exp_fcvtmod = 0,
|
||||
.exp_fcvtmod_fflags = FFLAG_NX },
|
||||
{ .name = "-value just above -1.0",
|
||||
.inp_lu = 0xbfefffffffffffff,
|
||||
.exp_fcvt = 0,
|
||||
.exp_fcvt_fflags = FFLAG_NX,
|
||||
.exp_fcvtmod = 0,
|
||||
.exp_fcvtmod_fflags = FFLAG_NX },
|
||||
|
||||
{ .name = "+1.0",
|
||||
.inp_lf = 0x1p0,
|
||||
.exp_fcvt = 0x0000000000000001,
|
||||
.exp_fcvt_fflags = 0,
|
||||
.exp_fcvtmod = 0x0000000000000001,
|
||||
.exp_fcvtmod_fflags = 0 },
|
||||
{ .name = "-1.0",
|
||||
.inp_lf = -0x1p0,
|
||||
.exp_fcvt = 0xffffffffffffffff,
|
||||
.exp_fcvt_fflags = 0,
|
||||
.exp_fcvtmod = 0xffffffffffffffff,
|
||||
.exp_fcvtmod_fflags = 0 },
|
||||
|
||||
{ .name = "+1.5",
|
||||
.inp_lu = 0x3ff8000000000000,
|
||||
.exp_fcvt = 1,
|
||||
.exp_fcvt_fflags = FFLAG_NX,
|
||||
.exp_fcvtmod = 1,
|
||||
.exp_fcvtmod_fflags = FFLAG_NX },
|
||||
{ .name = "-1.5",
|
||||
.inp_lu = 0xbff8000000000000,
|
||||
.exp_fcvt = 0xffffffffffffffff,
|
||||
.exp_fcvt_fflags = FFLAG_NX,
|
||||
.exp_fcvtmod = 0xffffffffffffffff,
|
||||
.exp_fcvtmod_fflags = FFLAG_NX },
|
||||
|
||||
{ .name = "+max int32 (2147483647)",
|
||||
.inp_lu = 0x41dfffffffc00000,
|
||||
.exp_fcvt = 0x000000007fffffff,
|
||||
.exp_fcvt_fflags = 0,
|
||||
.exp_fcvtmod = 0x000000007fffffff,
|
||||
.exp_fcvtmod_fflags = 0 },
|
||||
{ .name = "+max int32 +1 (2147483648)",
|
||||
.inp_lf = 0x1p31,
|
||||
.exp_fcvt = 0x000000007fffffff,
|
||||
.exp_fcvt_fflags = FFLAG_NV,
|
||||
.exp_fcvtmod = (uint64_t)-2147483648l, /* int32 min */
|
||||
.exp_fcvtmod_fflags = FFLAG_NV },
|
||||
{ .name = "+max int32 +2 (2147483649)",
|
||||
.inp_lu = 0x41e0000000200000,
|
||||
.exp_fcvt = 0x000000007fffffff,
|
||||
.exp_fcvt_fflags = FFLAG_NV,
|
||||
.exp_fcvtmod = (uint64_t)-2147483647l, /* int32 min +1 */
|
||||
.exp_fcvtmod_fflags = FFLAG_NV },
|
||||
|
||||
{ .name = "-max int32 (-2147483648)",
|
||||
.inp_lf = -0x1p31,
|
||||
.exp_fcvt = 0xffffffff80000000,
|
||||
.exp_fcvt_fflags = 0,
|
||||
.exp_fcvtmod = 0xffffffff80000000,
|
||||
.exp_fcvtmod_fflags = 0 },
|
||||
{ .name = "-max int32 -1 (-2147483649)",
|
||||
.inp_lf = -0x1.00000002p+31,
|
||||
.exp_fcvt = 0xffffffff80000000,
|
||||
.exp_fcvt_fflags = FFLAG_NV,
|
||||
.exp_fcvtmod = 2147483647, /* int32 max */
|
||||
.exp_fcvtmod_fflags = FFLAG_NV },
|
||||
{ .name = "-max int32 -2 (-2147483650)",
|
||||
.inp_lf = -0x1.00000004p+31,
|
||||
.exp_fcvt = 0xffffffff80000000,
|
||||
.exp_fcvt_fflags = FFLAG_NV,
|
||||
.exp_fcvtmod = 2147483646, /* int32 max -1 */
|
||||
.exp_fcvtmod_fflags = FFLAG_NV },
|
||||
};
|
||||
|
||||
int run_fcvtmod_tests()
|
||||
{
|
||||
uint64_t act_fcvt;
|
||||
uint8_t act_fcvt_fflags;
|
||||
uint64_t act_fcvtmod;
|
||||
uint8_t act_fcvtmod_fflags;
|
||||
|
||||
for (size_t i = 0; i < sizeof(tests)/sizeof(tests[0]); i++) {
|
||||
const fp64_fcvt_fcvtmod_testcase_t *t = &tests[i];
|
||||
|
||||
act_fcvt = do_fcvt_w_d(t->inp_lu, &act_fcvt_fflags);
|
||||
int fcvt_correct = act_fcvt == t->exp_fcvt &&
|
||||
act_fcvt_fflags == t->exp_fcvt_fflags;
|
||||
act_fcvtmod = do_fcvtmod_w_d(t->inp_lu, &act_fcvtmod_fflags);
|
||||
int fcvtmod_correct = act_fcvtmod == t->exp_fcvtmod &&
|
||||
act_fcvtmod_fflags == t->exp_fcvtmod_fflags;
|
||||
|
||||
if (fcvt_correct && fcvtmod_correct) {
|
||||
continue;
|
||||
}
|
||||
|
||||
printf("Test %zu (%s) failed!\n", i, t->name);
|
||||
|
||||
double fpr = do_fmv_d_x(t->inp_lu);
|
||||
printf("inp_lu: 0x%016lx == %lf\n", t->inp_lu, fpr);
|
||||
printf("inp_lf: %lf\n", t->inp_lf);
|
||||
|
||||
uint32_t sign = (t->inp_lu >> 63);
|
||||
uint32_t exp = (uint32_t)(t->inp_lu >> 52) & 0x7ff;
|
||||
uint64_t frac = t->inp_lu & 0xfffffffffffffull; /* significand */
|
||||
int true_exp = exp - 1023;
|
||||
int shift = true_exp - 52;
|
||||
uint64_t true_frac = frac | 1ull << 52;
|
||||
|
||||
printf("sign=%d, exp=0x%03x, frac=0x%012lx\n", sign, exp, frac);
|
||||
printf("true_exp=%d, shift=%d, true_frac=0x%016lx\n", true_exp, shift, true_frac);
|
||||
|
||||
if (!fcvt_correct) {
|
||||
printf("act_fcvt: 0x%016lx == %li\n", act_fcvt, act_fcvt);
|
||||
printf("exp_fcvt: 0x%016lx == %li\n", t->exp_fcvt, t->exp_fcvt);
|
||||
printf("act_fcvt_fflags: "); print_fflags(act_fcvt_fflags); printf("\n");
|
||||
printf("exp_fcvt_fflags: "); print_fflags(t->exp_fcvt_fflags); printf("\n");
|
||||
}
|
||||
|
||||
if (!fcvtmod_correct) {
|
||||
printf("act_fcvtmod: 0x%016lx == %li\n", act_fcvtmod, act_fcvtmod);
|
||||
printf("exp_fcvtmod: 0x%016lx == %li\n", t->exp_fcvtmod, t->exp_fcvtmod);
|
||||
printf("act_fcvtmod_fflags: "); print_fflags(act_fcvtmod_fflags); printf("\n");
|
||||
printf("exp_fcvtmod_fflags: "); print_fflags(t->exp_fcvtmod_fflags); printf("\n");
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int main()
|
||||
{
|
||||
return run_fcvtmod_tests();
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue