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Third RISC-V PR for 8.1
* Use xl instead of mxl for disassemble * Factor out extension tests to cpu_cfg.h * disas/riscv: Add vendor extension support * disas/riscv: Add support for XVentanaCondOps * disas/riscv: Add support for XThead* instructions * Fix mstatus related problems * Fix veyron-v1 CPU properties * Fix the xlen for data address when MPRV=1 * opensbi: Upgrade from v1.2 to v1.3 * Enable 32-bit Spike OpenSBI boot testing * Support the watchdog timer of HiFive 1 rev b * Only build qemu-system-riscv$$ on rv$$ host * Add RVV registers to log * Restrict ACLINT to TCG * Add syscall riscv_hwprobe * Add support for BF16 extensions * KVM_RISCV_SET_TIMER macro is not configured correctly * Generate devicetree only after machine initialization is complete * virt: Convert fdt_load_addr to uint64_t * KVM: fixes and enhancements * Add support for the Zfa extension -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmSr+ekACgkQr3yVEwxT gBMMGg//ZCcyH3KXB49c2KUIFO6FKYUxN9uC3giZCtuGyEH8T2yDgZVVXnxwU+Ij +3Ej6T/ZdWMpePC9qf+xKzHWZk7Qc8Tcg+JgQbga573894yZInRwYl8HsSlEKA+Z vlqSBPxTlp9rlDwGP/LjGljyIFqL4konk9zi3FL4ZXTF1iHUGrh/953Y3wIreEfl KX5UznnWcgy2BqQT1vihMbM8qCVK6iryH+QZ6LiAsPMSX1rIzk8ectQryILzoIYh bMiwCLVMyr4ZrUXjmGTF+7/WcOWwhhyfpdstf2iotKALelZtVHit0wHcty2GYQde nvN83jJWu04DGXkPBUsqCUQXczGo1QHjJUH3RIRJzfOby/lGt4pSzHAfKA+iNUht ikM3SdBsXMO+ogjTtTcCMb7/m2vsMoQP60VRts9Mh3YVD0cgr7RqpqRoEMugVYnr ca8Vijf71mB+y+pq477eV1Q8BoKpr8xa1OlFkNKPC17uMD7HoDMI44QgFOgtYp10 TMsqqyB75q6PZhSEwm63xbmH0Zpo8kSqT/E3MTtGTyPeuL8TNNNSkCmFaGYmRrbI XEp7vG2RaDJOvDomS3nUhA5ruc8SaXd0q25q2gLYQfCsehfFqZAwuNB5xf1zS0M0 ov1/gwaqU93t6nLbo2cCbb0plkIFKwwJ9KKjD06wJ4KPe0TGFzk= =3XFD -----END PGP SIGNATURE----- Merge tag 'pull-riscv-to-apply-20230710-1' of https://github.com/alistair23/qemu into staging Third RISC-V PR for 8.1 * Use xl instead of mxl for disassemble * Factor out extension tests to cpu_cfg.h * disas/riscv: Add vendor extension support * disas/riscv: Add support for XVentanaCondOps * disas/riscv: Add support for XThead* instructions * Fix mstatus related problems * Fix veyron-v1 CPU properties * Fix the xlen for data address when MPRV=1 * opensbi: Upgrade from v1.2 to v1.3 * Enable 32-bit Spike OpenSBI boot testing * Support the watchdog timer of HiFive 1 rev b * Only build qemu-system-riscv$$ on rv$$ host * Add RVV registers to log * Restrict ACLINT to TCG * Add syscall riscv_hwprobe * Add support for BF16 extensions * KVM_RISCV_SET_TIMER macro is not configured correctly * Generate devicetree only after machine initialization is complete * virt: Convert fdt_load_addr to uint64_t * KVM: fixes and enhancements * Add support for the Zfa extension # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmSr+ekACgkQr3yVEwxT # gBMMGg//ZCcyH3KXB49c2KUIFO6FKYUxN9uC3giZCtuGyEH8T2yDgZVVXnxwU+Ij # +3Ej6T/ZdWMpePC9qf+xKzHWZk7Qc8Tcg+JgQbga573894yZInRwYl8HsSlEKA+Z # vlqSBPxTlp9rlDwGP/LjGljyIFqL4konk9zi3FL4ZXTF1iHUGrh/953Y3wIreEfl # KX5UznnWcgy2BqQT1vihMbM8qCVK6iryH+QZ6LiAsPMSX1rIzk8ectQryILzoIYh # bMiwCLVMyr4ZrUXjmGTF+7/WcOWwhhyfpdstf2iotKALelZtVHit0wHcty2GYQde # nvN83jJWu04DGXkPBUsqCUQXczGo1QHjJUH3RIRJzfOby/lGt4pSzHAfKA+iNUht # ikM3SdBsXMO+ogjTtTcCMb7/m2vsMoQP60VRts9Mh3YVD0cgr7RqpqRoEMugVYnr # ca8Vijf71mB+y+pq477eV1Q8BoKpr8xa1OlFkNKPC17uMD7HoDMI44QgFOgtYp10 # TMsqqyB75q6PZhSEwm63xbmH0Zpo8kSqT/E3MTtGTyPeuL8TNNNSkCmFaGYmRrbI # XEp7vG2RaDJOvDomS3nUhA5ruc8SaXd0q25q2gLYQfCsehfFqZAwuNB5xf1zS0M0 # ov1/gwaqU93t6nLbo2cCbb0plkIFKwwJ9KKjD06wJ4KPe0TGFzk= # =3XFD # -----END PGP SIGNATURE----- # gpg: Signature made Mon 10 Jul 2023 01:30:33 PM BST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20230710-1' of https://github.com/alistair23/qemu: (54 commits) riscv: Add support for the Zfa extension target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper target/riscv: update multi-letter extension KVM properties target/riscv/cpu.c: create KVM mock properties target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext() target/riscv/cpu.c: add satp_mode properties earlier target/riscv/kvm.c: add multi-letter extension KVM properties target/riscv/kvm.c: update KVM MISA bits target/riscv: add KVM specific MISA properties target/riscv/cpu: add misa_ext_info_arr[] target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids() target/riscv: use KVM scratch CPUs to init KVM properties target/riscv/cpu.c: restrict 'marchid' value target/riscv/cpu.c: restrict 'mimpid' value target/riscv/cpu.c: restrict 'mvendorid' value hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set target/riscv: skip features setup for KVM CPUs ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
commit
94d68c1136
44 changed files with 4751 additions and 442 deletions
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@ -228,6 +228,7 @@
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#define TARGET_NR_accept4 242
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#define TARGET_NR_arch_specific_syscall 244
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#define TARGET_NR_riscv_flush_icache (TARGET_NR_arch_specific_syscall + 15)
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#define TARGET_NR_riscv_hwprobe (TARGET_NR_arch_specific_syscall + 14)
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#define TARGET_NR_prlimit64 261
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#define TARGET_NR_fanotify_init 262
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#define TARGET_NR_fanotify_mark 263
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@ -251,6 +251,7 @@
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#define TARGET_NR_recvmmsg 243
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#define TARGET_NR_arch_specific_syscall 244
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#define TARGET_NR_riscv_flush_icache (TARGET_NR_arch_specific_syscall + 15)
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#define TARGET_NR_riscv_hwprobe (TARGET_NR_arch_specific_syscall + 14)
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#define TARGET_NR_wait4 260
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#define TARGET_NR_prlimit64 261
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#define TARGET_NR_fanotify_init 262
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@ -8983,6 +8983,147 @@ static int do_getdents64(abi_long dirfd, abi_long arg2, abi_long count)
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}
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#endif /* TARGET_NR_getdents64 */
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#if defined(TARGET_NR_riscv_hwprobe)
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#define RISCV_HWPROBE_KEY_MVENDORID 0
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#define RISCV_HWPROBE_KEY_MARCHID 1
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#define RISCV_HWPROBE_KEY_MIMPID 2
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#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
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#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0)
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#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
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#define RISCV_HWPROBE_IMA_FD (1 << 0)
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#define RISCV_HWPROBE_IMA_C (1 << 1)
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#define RISCV_HWPROBE_KEY_CPUPERF_0 5
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#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
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#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
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#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0)
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#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0)
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#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
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#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
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struct riscv_hwprobe {
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abi_llong key;
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abi_ullong value;
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};
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static void risc_hwprobe_fill_pairs(CPURISCVState *env,
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struct riscv_hwprobe *pair,
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size_t pair_count)
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{
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const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
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for (; pair_count > 0; pair_count--, pair++) {
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abi_llong key;
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abi_ullong value;
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__put_user(0, &pair->value);
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__get_user(key, &pair->key);
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switch (key) {
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case RISCV_HWPROBE_KEY_MVENDORID:
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__put_user(cfg->mvendorid, &pair->value);
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break;
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case RISCV_HWPROBE_KEY_MARCHID:
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__put_user(cfg->marchid, &pair->value);
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break;
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case RISCV_HWPROBE_KEY_MIMPID:
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__put_user(cfg->mimpid, &pair->value);
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break;
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case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
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value = riscv_has_ext(env, RVI) &&
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riscv_has_ext(env, RVM) &&
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riscv_has_ext(env, RVA) ?
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RISCV_HWPROBE_BASE_BEHAVIOR_IMA : 0;
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__put_user(value, &pair->value);
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break;
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case RISCV_HWPROBE_KEY_IMA_EXT_0:
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value = riscv_has_ext(env, RVF) &&
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riscv_has_ext(env, RVD) ?
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RISCV_HWPROBE_IMA_FD : 0;
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value |= riscv_has_ext(env, RVC) ?
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RISCV_HWPROBE_IMA_C : pair->value;
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__put_user(value, &pair->value);
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break;
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case RISCV_HWPROBE_KEY_CPUPERF_0:
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__put_user(RISCV_HWPROBE_MISALIGNED_FAST, &pair->value);
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break;
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default:
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__put_user(-1, &pair->key);
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break;
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}
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}
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}
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static int cpu_set_valid(abi_long arg3, abi_long arg4)
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{
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int ret, i, tmp;
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size_t host_mask_size, target_mask_size;
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unsigned long *host_mask;
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/*
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* cpu_set_t represent CPU masks as bit masks of type unsigned long *.
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* arg3 contains the cpu count.
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*/
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tmp = (8 * sizeof(abi_ulong));
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target_mask_size = ((arg3 + tmp - 1) / tmp) * sizeof(abi_ulong);
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host_mask_size = (target_mask_size + (sizeof(*host_mask) - 1)) &
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~(sizeof(*host_mask) - 1);
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host_mask = alloca(host_mask_size);
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ret = target_to_host_cpu_mask(host_mask, host_mask_size,
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arg4, target_mask_size);
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if (ret != 0) {
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return ret;
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}
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for (i = 0 ; i < host_mask_size / sizeof(*host_mask); i++) {
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if (host_mask[i] != 0) {
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return 0;
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}
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}
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return -TARGET_EINVAL;
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}
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static abi_long do_riscv_hwprobe(CPUArchState *cpu_env, abi_long arg1,
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abi_long arg2, abi_long arg3,
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abi_long arg4, abi_long arg5)
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{
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int ret;
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struct riscv_hwprobe *host_pairs;
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/* flags must be 0 */
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if (arg5 != 0) {
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return -TARGET_EINVAL;
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}
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/* check cpu_set */
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if (arg3 != 0) {
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ret = cpu_set_valid(arg3, arg4);
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if (ret != 0) {
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return ret;
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}
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} else if (arg4 != 0) {
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return -TARGET_EINVAL;
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}
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/* no pairs */
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if (arg2 == 0) {
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return 0;
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}
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host_pairs = lock_user(VERIFY_WRITE, arg1,
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sizeof(*host_pairs) * (size_t)arg2, 0);
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if (host_pairs == NULL) {
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return -TARGET_EFAULT;
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}
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risc_hwprobe_fill_pairs(cpu_env, host_pairs, arg2);
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unlock_user(host_pairs, arg1, sizeof(*host_pairs) * (size_t)arg2);
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return 0;
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}
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#endif /* TARGET_NR_riscv_hwprobe */
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#if defined(TARGET_NR_pivot_root) && defined(__NR_pivot_root)
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_syscall2(int, pivot_root, const char *, new_root, const char *, put_old)
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#endif
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@ -13665,6 +13806,11 @@ static abi_long do_syscall1(CPUArchState *cpu_env, int num, abi_long arg1,
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return ret;
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#endif
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#if defined(TARGET_NR_riscv_hwprobe)
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case TARGET_NR_riscv_hwprobe:
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return do_riscv_hwprobe(cpu_env, arg1, arg2, arg3, arg4, arg5);
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#endif
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default:
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qemu_log_mask(LOG_UNIMP, "Unsupported syscall: %d\n", num);
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return -TARGET_ENOSYS;
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