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esp: checkpatch fixes

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Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20210304221103.6369-2-mark.cave-ayland@ilande.co.uk>
This commit is contained in:
Mark Cave-Ayland 2021-03-04 22:10:22 +00:00
parent 91e92cad67
commit 94d5c79d32
1 changed files with 31 additions and 21 deletions
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40
hw/scsi/esp.c
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@ -241,9 +241,10 @@ static void handle_satn(ESPState *s)
}
s->pdma_cb = satn_pdma_cb;
len = get_cmd(s, buf, sizeof(buf));
if (len)
if (len) {
do_cmd(s, buf);
}
}
static void s_without_satn_pdma_cb(ESPState *s)
{
@ -445,15 +446,18 @@ static void esp_do_dma(ESPState *s)
s->dma_left -= len;
s->async_buf += len;
s->async_len -= len;
if (to_device)
if (to_device) {
s->ti_size += len;
else
} else {
s->ti_size -= len;
}
if (s->async_len == 0) {
scsi_req_continue(s->current_req);
/* If there is still data to be read from the device then
complete the DMA operation immediately. Otherwise defer
until the scsi layer has completed. */
/*
* If there is still data to be read from the device then
* complete the DMA operation immediately. Otherwise defer
* until the scsi layer has completed.
*/
if (to_device || s->dma_left != 0 || s->ti_size == 0) {
return;
}
@ -490,7 +494,8 @@ void esp_command_complete(SCSIRequest *req, size_t resid)
ESPState *s = req->hba_private;
if (s->rregs[ESP_RSTAT] & STAT_INT) {
/* Defer handling command complete until the previous
/*
* Defer handling command complete until the previous
* interrupt has been handled.
*/
trace_esp_command_complete_deferred();
@ -512,8 +517,10 @@ void esp_transfer_data(SCSIRequest *req, uint32_t len)
if (s->dma_left) {
esp_do_dma(s);
} else if (s->dma_counter != 0 && s->ti_size <= 0) {
/* If this was the last part of a DMA transfer then the
completion interrupt is deferred to here. */
/*
* If this was the last part of a DMA transfer then the
* completion interrupt is deferred to here.
*/
esp_dma_done(s);
}
}
@ -535,12 +542,13 @@ static void handle_ti(ESPState *s)
}
s->dma_counter = dmalen;
if (s->do_cmd)
if (s->do_cmd) {
minlen = (dmalen < ESP_CMDBUF_SZ) ? dmalen : ESP_CMDBUF_SZ;
else if (s->ti_size < 0)
} else if (s->ti_size < 0) {
minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
else
} else {
minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
}
trace_esp_handle_ti(minlen);
if (s->dma) {
s->dma_left = minlen;
@ -605,8 +613,10 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
}
break;
case ESP_RINTR:
/* Clear sequence step, interrupt register and all status bits
except TC */
/*
* Clear sequence step, interrupt register and all status bits
* except TC
*/
old_val = s->rregs[ESP_RINTR];
s->rregs[ESP_RINTR] = 0;
s->rregs[ESP_RSTAT] &= ~STAT_TC;
@ -670,7 +680,7 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
break;
case CMD_FLUSH:
trace_esp_mem_writeb_cmd_flush(val);
//s->ti_size = 0;
/*s->ti_size = 0;*/
s->rregs[ESP_RINTR] = INTR_FC;
s->rregs[ESP_RSEQ] = 0;
s->rregs[ESP_RFLAGS] = 0;