mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-11 03:24:58 -06:00
x86: add support for second ioapic
Add ioapic_init_secondary to initialize it, wire up in gsi handling and acpi apic table creation. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Message-id: 20201203105423.10431-4-kraxel@redhat.com
This commit is contained in:
parent
ceea95cd88
commit
94c5a60637
5 changed files with 37 additions and 1 deletions
|
@ -22,6 +22,8 @@
|
|||
|
||||
#define IOAPIC_NUM_PINS 24
|
||||
#define IO_APIC_DEFAULT_ADDRESS 0xfec00000
|
||||
#define IO_APIC_SECONDARY_ADDRESS (IO_APIC_DEFAULT_ADDRESS + 0x10000)
|
||||
#define IO_APIC_SECONDARY_IRQBASE 24 /* primary 0 -> 23, secondary 24 -> 47 */
|
||||
|
||||
#define TYPE_KVM_IOAPIC "kvm-ioapic"
|
||||
#define TYPE_IOAPIC "ioapic"
|
||||
|
|
|
@ -27,7 +27,7 @@
|
|||
#include "qemu/notify.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define MAX_IOAPICS 1
|
||||
#define MAX_IOAPICS 2
|
||||
|
||||
#define IOAPIC_LVT_DEST_SHIFT 56
|
||||
#define IOAPIC_LVT_DEST_IDX_SHIFT 48
|
||||
|
|
|
@ -50,6 +50,7 @@ struct X86MachineState {
|
|||
ISADevice *rtc;
|
||||
FWCfgState *fw_cfg;
|
||||
qemu_irq *gsi;
|
||||
DeviceState *ioapic2;
|
||||
GMappedFile *initrd_mapped_file;
|
||||
HotplugHandler *acpi_dev;
|
||||
|
||||
|
@ -120,10 +121,12 @@ bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms);
|
|||
typedef struct GSIState {
|
||||
qemu_irq i8259_irq[ISA_NUM_IRQS];
|
||||
qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
|
||||
qemu_irq ioapic2_irq[IOAPIC_NUM_PINS];
|
||||
} GSIState;
|
||||
|
||||
qemu_irq x86_allocate_cpu_irq(void);
|
||||
void gsi_handler(void *opaque, int n, int level);
|
||||
void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
|
||||
DeviceState *ioapic_init_secondary(GSIState *gsi_state);
|
||||
|
||||
#endif
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue