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target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs

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Replace type2_trigger_t with the real tdata1, tdata2, and tdata3 CSRs,
which allows us to support more types of triggers in the future.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20220909134215.1843865-4-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2022-09-09 21:42:10 +08:00 • committed by Alistair Francis
parent 9d5a84db91
commit 9495c4888a
4 changed files with 48 additions and 88 deletions
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7
target/riscv/debug.h
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@ -44,13 +44,6 @@ typedef enum {
TRIGGER_TYPE_NUM
} trigger_type_t;
typedef struct {
target_ulong mcontrol;
target_ulong maddress;
struct CPUBreakpoint *bp;
struct CPUWatchpoint *wp;
} type2_trigger_t;
/* tdata1 field masks */
#define RV32_TYPE(t) ((uint32_t)(t) << 28)