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target-mips: add TLBINV support

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For Standard TLB configuration (Config.MT=1):

TLBINV invalidates a set of TLB entries based on ASID. The virtual address is
ignored in the entry match. TLB entries which have their G bit set to 1 are not
modified.

TLBINVF causes all entries to be invalidated.

Single TLB entry can be marked as invalid on TLB entry write by having
EntryHi.EHINV set to 1.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
This commit is contained in:
Leon Alrae 2014-07-07 11:24:00 +01:00
parent 92ceb440d4
commit 9456c2fbcd
7 changed files with 94 additions and 8 deletions
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2
disas/mips.c
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@ -2410,6 +2410,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 },
{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 },
{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 },
{"tlbinv", "", 0x42000003, 0xffffffff, INSN_TLB, 0, I32 },
{"tlbinvf", "", 0x42000004, 0xffffffff, INSN_TLB, 0, I32 },
{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1 },
{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },