mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-06 17:23:56 -06:00
Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevel global variables to use the new qemu_log*() macros. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6338 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aliguori
parent
6cec548799
commit
93fcfe39a0
40 changed files with 293 additions and 469 deletions
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@ -117,10 +117,7 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
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int ret = TLBRET_MATCH;
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#if 0
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if (logfile) {
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fprintf(logfile, "user mode %d h %08x\n",
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user_mode, env->hflags);
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}
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qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
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#endif
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if (address <= (int32_t)0x7FFFFFFFUL) {
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@ -198,9 +195,8 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
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}
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}
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#if 0
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if (logfile) {
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fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
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address, rw, access_type, *physical, *prot, ret);
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qemu_log(TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
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address, rw, access_type, *physical, *prot, ret);
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}
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#endif
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@ -233,13 +229,11 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int access_type;
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int ret = 0;
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if (logfile) {
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#if 0
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cpu_dump_state(env, logfile, fprintf, 0);
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log_cpu_state(env, 0);
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#endif
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fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n",
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__func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu);
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}
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qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n",
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__func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu);
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rw &= 1;
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@ -252,10 +246,8 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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#else
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ret = get_physical_address(env, &physical, &prot,
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address, rw, access_type);
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if (logfile) {
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fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",
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__func__, address, ret, physical, prot);
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}
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qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",
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__func__, address, ret, physical, prot);
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if (ret == TLBRET_MATCH) {
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ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
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physical & TARGET_PAGE_MASK, prot,
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@ -357,14 +349,14 @@ void do_interrupt (CPUState *env)
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int cause = -1;
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const char *name;
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if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
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if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
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if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
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name = "unknown";
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else
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name = excp_names[env->exception_index];
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fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
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__func__, env->active_tc.PC, env->CP0_EPC, name);
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qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
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__func__, env->active_tc.PC, env->CP0_EPC, name);
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}
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if (env->exception_index == EXCP_EXT_INTERRUPT &&
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(env->hflags & MIPS_HFLAG_DM))
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@ -558,15 +550,12 @@ void do_interrupt (CPUState *env)
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env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
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break;
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default:
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if (logfile) {
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fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
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env->exception_index);
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}
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qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index);
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printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
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exit(1);
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}
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if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
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fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
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if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
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qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
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" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
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__func__, env->active_tc.PC, env->CP0_EPC, cause,
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env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
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@ -29,8 +29,8 @@
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void do_raise_exception_err (uint32_t exception, int error_code)
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{
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#if 1
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if (logfile && exception < 0x100)
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fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
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if (exception < 0x100)
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qemu_log("%s: %d %d\n", __func__, exception, error_code);
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#endif
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env->exception_index = exception;
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env->error_code = error_code;
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@ -1342,21 +1342,21 @@ void do_mtc0_datahi (target_ulong t0)
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void do_mtc0_status_debug(uint32_t old, uint32_t val)
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{
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fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
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qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
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old, old & env->CP0_Cause & CP0Ca_IP_mask,
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val, val & env->CP0_Cause & CP0Ca_IP_mask,
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env->CP0_Cause);
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switch (env->hflags & MIPS_HFLAG_KSU) {
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case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
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case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
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case MIPS_HFLAG_KM: fputs("\n", logfile); break;
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case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
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case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
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case MIPS_HFLAG_KM: qemu_log("\n"); break;
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default: cpu_abort(env, "Invalid MMU mode!\n"); break;
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}
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}
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void do_mtc0_status_irqraise_debug(void)
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{
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fprintf(logfile, "Raise pending IRQs\n");
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qemu_log("Raise pending IRQs\n");
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}
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/* MIPS MT functions */
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@ -1705,35 +1705,38 @@ target_ulong do_ei (void)
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static void debug_pre_eret (void)
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{
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fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
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env->active_tc.PC, env->CP0_EPC);
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if (env->CP0_Status & (1 << CP0St_ERL))
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fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
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if (env->hflags & MIPS_HFLAG_DM)
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fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
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fputs("\n", logfile);
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if (loglevel & CPU_LOG_EXEC) {
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qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
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env->active_tc.PC, env->CP0_EPC);
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if (env->CP0_Status & (1 << CP0St_ERL))
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qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
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if (env->hflags & MIPS_HFLAG_DM)
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qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
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qemu_log("\n");
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}
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}
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static void debug_post_eret (void)
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{
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fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
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env->active_tc.PC, env->CP0_EPC);
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if (env->CP0_Status & (1 << CP0St_ERL))
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fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
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if (env->hflags & MIPS_HFLAG_DM)
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fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
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switch (env->hflags & MIPS_HFLAG_KSU) {
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case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
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case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
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case MIPS_HFLAG_KM: fputs("\n", logfile); break;
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default: cpu_abort(env, "Invalid MMU mode!\n"); break;
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if (loglevel & CPU_LOG_EXEC) {
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qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
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env->active_tc.PC, env->CP0_EPC);
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if (env->CP0_Status & (1 << CP0St_ERL))
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qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
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if (env->hflags & MIPS_HFLAG_DM)
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qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
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switch (env->hflags & MIPS_HFLAG_KSU) {
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case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
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case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
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case MIPS_HFLAG_KM: qemu_log("\n"); break;
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default: cpu_abort(env, "Invalid MMU mode!\n"); break;
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}
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}
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}
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void do_eret (void)
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{
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if (loglevel & CPU_LOG_EXEC)
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debug_pre_eret();
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debug_pre_eret();
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if (env->CP0_Status & (1 << CP0St_ERL)) {
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env->active_tc.PC = env->CP0_ErrorEPC;
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env->CP0_Status &= ~(1 << CP0St_ERL);
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@ -1742,20 +1745,17 @@ void do_eret (void)
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env->CP0_Status &= ~(1 << CP0St_EXL);
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}
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compute_hflags(env);
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if (loglevel & CPU_LOG_EXEC)
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debug_post_eret();
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debug_post_eret();
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env->CP0_LLAddr = 1;
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}
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void do_deret (void)
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{
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if (loglevel & CPU_LOG_EXEC)
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debug_pre_eret();
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debug_pre_eret();
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env->active_tc.PC = env->CP0_DEPC;
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env->hflags &= MIPS_HFLAG_DM;
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compute_hflags(env);
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if (loglevel & CPU_LOG_EXEC)
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debug_post_eret();
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debug_post_eret();
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env->CP0_LLAddr = 1;
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}
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#endif /* !CONFIG_USER_ONLY */
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@ -514,18 +514,11 @@ static const char *fregnames_h[] =
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"h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", };
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#ifdef MIPS_DEBUG_DISAS
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#define MIPS_DEBUG(fmt, args...) \
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do { \
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if (loglevel & CPU_LOG_TB_IN_ASM) { \
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fprintf(logfile, TARGET_FMT_lx ": %08x " fmt "\n", \
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ctx->pc, ctx->opcode , ##args); \
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} \
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} while (0)
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#define LOG_DISAS(...) \
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do { \
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if (loglevel & CPU_LOG_TB_IN_ASM) \
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fprintf(logfile, ## __VA_ARGS__); \
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} while (0)
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#define MIPS_DEBUG(fmt, args...) \
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qemu_log_mask(CPU_LOG_TB_IN_ASM, \
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TARGET_FMT_lx ": %08x " fmt "\n", \
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ctx->pc, ctx->opcode , ##args)
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#define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
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#else
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#define MIPS_DEBUG(fmt, args...) do { } while(0)
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#define LOG_DISAS(...) do { } while (0)
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@ -8180,8 +8173,8 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
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int num_insns;
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int max_insns;
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if (search_pc && loglevel)
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fprintf (logfile, "search pc %d\n", search_pc);
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if (search_pc)
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qemu_log("search pc %d\n", search_pc);
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pc_start = tb->pc;
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/* Leave some spare opc slots for branch handling. */
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@ -8203,11 +8196,9 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
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if (max_insns == 0)
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max_insns = CF_COUNT_MASK;
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#ifdef DEBUG_DISAS
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if (loglevel & CPU_LOG_TB_CPU) {
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fprintf(logfile, "------------------------------------------------\n");
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/* FIXME: This may print out stale hflags from env... */
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cpu_dump_state(env, logfile, fprintf, 0);
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}
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qemu_log_mask(CPU_LOG_TB_CPU, "------------------------------------------------\n");
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/* FIXME: This may print out stale hflags from env... */
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log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
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#endif
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LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
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gen_icount_start();
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@ -8299,13 +8290,11 @@ done_generating:
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#ifdef DEBUG_DISAS
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LOG_DISAS("\n");
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if (loglevel & CPU_LOG_TB_IN_ASM) {
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fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
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target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
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fprintf(logfile, "\n");
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}
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if (loglevel & CPU_LOG_TB_CPU) {
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fprintf(logfile, "---------------- %d %08x\n", ctx.bstate, ctx.hflags);
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qemu_log("IN: %s\n", lookup_symbol(pc_start));
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log_target_disas(pc_start, ctx.pc - pc_start, 0);
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qemu_log("\n");
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}
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qemu_log_mask(CPU_LOG_TB_CPU, "---------------- %d %08x\n", ctx.bstate, ctx.hflags);
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#endif
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}
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