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ppc 7.0 queue:
* General cleanup for Mac machines (Peter) * Fixes for FPU exceptions (Lucas) * Support for new ISA31 instructions (Matheus) * Fixes for ivshmem (Daniel) * Cleanups for PowerNV PHB (Christophe and Cedric) * Updates of PowerNV and pSeries documentation (Leonardo and Daniel) * Fixes for PowerNV (Daniel) * Large cleanup of FPU implementation (Richard) * Removal of SoftTLBs support for PPC74x CPUs (Fabiano) * Fixes for exception models in MPCx and 60x CPUs (Fabiano) * Removal of 401/403 CPUs (Cedric) * Deprecation of taihu machine (Thomas) * Large rework of PPC405 machine (Cedric) * Fixes for VSX instructions (Victor and Matheus) * Fix for e6500 CPU (Fabiano) * Initial support for PMU (Daniel) -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmG8xt8ACgkQUaNDx8/7 7KG3Dg/9EXK3GslNgUNRvB1pgRSimnrUirGUiDmZPXxevIbsoPsYaXmUcD1zOnlb zXiCzQ2Bvi8ZUjT1uScP7dkFCdzs6gXYbTEcTzscX3k2VnTjXHXhQ3cnb0uModP5 U1QzrjV7K/q1usJW5OVSGZS1PoWOqWuZNdcp0mIUWcJHhSaYtUGGPohp7rH0JSug ncmkRA0KLgIX8eg8swyfJxrw9wCcXlFIcmwHipB8S/Dd/gUpmFEoaQsmugSJNYZe zi8Fd4jfzlRXVwb8EUSiOiaXSd/WKjEcQx/usbzzaBacbktk/nfy+rligUMryCpO vGFM5blxEX5SXD3Cd0vcFwYhCZImphD8K+Sxe6Us69rsUH11hJS+q29/Puk1MkHt DTubqB3k4BheiatOV1zeUMlbRm5svUhGj3VstFZYZeZ3Oh47Jsx3XH4hoytUuc/1 lP9UGkaf3nIx12vSqBA/3Crc7zalWX5OhaUV5RG30+jxd8zHOKcasKbd22710DNz 4WybQLb3bpUr091mWMKcaAkP6bxcE8S+mR4LE2kdELboAnkB+OgSmrdZ3slceaCv btV8qjNl4f8lBvyFQVxZ5bn05+TfxUXFlFxXipxf1fI64bYwRnyQQ3yRxMHipRYK CRta1akVgIgcBbeeRHBZLA12UgTQJY6WIoDaZMz9NxIDHJnX/jw= =APFd -----END PGP SIGNATURE----- Merge tag 'pull-ppc-20211217' of https://github.com/legoater/qemu into staging ppc 7.0 queue: * General cleanup for Mac machines (Peter) * Fixes for FPU exceptions (Lucas) * Support for new ISA31 instructions (Matheus) * Fixes for ivshmem (Daniel) * Cleanups for PowerNV PHB (Christophe and Cedric) * Updates of PowerNV and pSeries documentation (Leonardo and Daniel) * Fixes for PowerNV (Daniel) * Large cleanup of FPU implementation (Richard) * Removal of SoftTLBs support for PPC74x CPUs (Fabiano) * Fixes for exception models in MPCx and 60x CPUs (Fabiano) * Removal of 401/403 CPUs (Cedric) * Deprecation of taihu machine (Thomas) * Large rework of PPC405 machine (Cedric) * Fixes for VSX instructions (Victor and Matheus) * Fix for e6500 CPU (Fabiano) * Initial support for PMU (Daniel) # gpg: Signature made Fri 17 Dec 2021 09:20:31 AM PST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-ppc-20211217' of https://github.com/legoater/qemu: (101 commits) ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices ppc/pnv: Move realize of PEC stacks under the PEC model ppc/pnv: Remove "system-memory" property from PHB4 PEC ppc/pnv: Compute the PHB index from the PHB4 PEC model ppc/pnv: Introduce a num_stack class attribute ppc/pnv: Introduce a "chip" property under the PHB4 model ppc/pnv: Introduce version and device_id class atributes for PHB4 devices ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices ppc/pnv: Use QOM hierarchy to scan PHB3 devices ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize() ppc/pnv: Drop the "num-phbs" property ppc/pnv: Use the chip class to check the index of PHB3 devices ppc/pnv: Introduce a "chip" property under PHB3 PPC64/TCG: Implement 'rfebb' instruction target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event target/ppc: enable PMU instruction count target/ppc: enable PMU counter overflow with cycle events target/ppc: PMU: update counters on MMCR1 write target/ppc: PMU: update counters on PMCs r/w target/ppc: PMU basic cycle count for pseries TCG ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
commit
93dc314c92
59 changed files with 2513 additions and 1646 deletions
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@ -11,6 +11,7 @@ endif
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bcdsub: CFLAGS += -mpower8-vector
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PPC64_TESTS += byte_reverse
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PPC64_TESTS += mtfsf
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ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_POWER10),)
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run-byte_reverse: QEMU_OPTS+=-cpu POWER10
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run-plugin-byte_reverse-with-%: QEMU_OPTS+=-cpu POWER10
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@ -16,6 +16,7 @@ byte_reverse: CFLAGS += -mcpu=power10
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run-byte_reverse: QEMU_OPTS+=-cpu POWER10
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run-plugin-byte_reverse-with-%: QEMU_OPTS+=-cpu POWER10
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PPC64LE_TESTS += mtfsf
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PPC64LE_TESTS += signal_save_restore_xer
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TESTS += $(PPC64LE_TESTS)
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61
tests/tcg/ppc64le/mtfsf.c
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61
tests/tcg/ppc64le/mtfsf.c
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@ -0,0 +1,61 @@
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#include <stdlib.h>
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#include <assert.h>
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#include <signal.h>
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#include <sys/prctl.h>
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#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
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#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
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#define FPSCR_FI 17 /* Floating-point fraction inexact */
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#define FP_VE (1ull << FPSCR_VE)
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#define FP_VXSOFT (1ull << FPSCR_VXSOFT)
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#define FP_FI (1ull << FPSCR_FI)
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void sigfpe_handler(int sig, siginfo_t *si, void *ucontext)
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{
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if (si->si_code == FPE_FLTINV) {
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exit(0);
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}
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exit(1);
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}
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int main(void)
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{
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union {
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double d;
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long long ll;
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} fpscr;
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struct sigaction sa = {
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.sa_sigaction = sigfpe_handler,
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.sa_flags = SA_SIGINFO
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};
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/*
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* Enable the MSR bits F0 and F1 to enable exceptions.
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* This shouldn't be needed in linux-user as these bits are enabled by
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* default, but this allows to execute either in a VM or a real machine
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* to compare the behaviors.
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*/
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prctl(PR_SET_FPEXC, PR_FP_EXC_PRECISE);
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/* First test if the FI bit is being set correctly */
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fpscr.ll = FP_FI;
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__builtin_mtfsf(0b11111111, fpscr.d);
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fpscr.d = __builtin_mffs();
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assert((fpscr.ll & FP_FI) != 0);
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/* Then test if the deferred exception is being called correctly */
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sigaction(SIGFPE, &sa, NULL);
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/*
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* Although the VXSOFT exception has been chosen, based on test in a Power9
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* any combination of exception bit + its enabling bit should work.
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* But if a different exception is chosen si_code check should
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* change accordingly.
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*/
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fpscr.ll = FP_VE | FP_VXSOFT;
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__builtin_mtfsf(0b11111111, fpscr.d);
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return 1;
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}
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