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pull-loongarch-20231013

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Merge tag 'pull-loongarch-20231013' of https://gitlab.com/gaosong/qemu into staging

pull-loongarch-20231013

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* tag 'pull-loongarch-20231013' of https://gitlab.com/gaosong/qemu:
  LoongArch: step down as general arch maintainer
  hw/loongarch/virt: Remove unused 'loongarch_virt_pm' region
  hw/loongarch/virt: Remove unused ISA Bus
  hw/loongarch/virt: Remove unused ISA UART
  hw/loongarch: remove global loaderparams variable
  target/loongarch: Add preldx instruction
  target/loongarch: fix ASXE flag conflict

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2023-10-16 12:37:35 -04:00
commit 9390f0fd3e
9 changed files with 49 additions and 87 deletions
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4
target/loongarch/cpu.h
View file

@ -458,11 +458,11 @@ static inline void set_pc(CPULoongArchState *env, uint64_t value)
* LoongArch CPUs hardware flags.
*/
#define HW_FLAGS_PLV_MASK R_CSR_CRMD_PLV_MASK /* 0x03 */
#define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */
#define HW_FLAGS_EUEN_FPE 0x04
#define HW_FLAGS_EUEN_SXE 0x08
#define HW_FLAGS_EUEN_ASXE 0x10
#define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */
#define HW_FLAGS_VA32 0x20
#define HW_FLAGS_EUEN_ASXE 0x40
static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *flags)

7
target/loongarch/disas.c
View file

@ -190,6 +190,12 @@ static void output_hint_r_i(DisasContext *ctx, arg_hint_r_i *a,
output(ctx, mnemonic, "%d, r%d, %d", a->hint, a->rj, a->imm);
}
static void output_hint_rr(DisasContext *ctx, arg_hint_rr *a,
const char *mnemonic)
{
output(ctx, mnemonic, "%d, r%d, r%d", a->hint, a->rj, a->rk);
}
static void output_i(DisasContext *ctx, arg_i *a, const char *mnemonic)
{
output(ctx, mnemonic, "%d", a->imm);
@ -549,6 +555,7 @@ INSN(ld_bu, rr_i)
INSN(ld_hu, rr_i)
INSN(ld_wu, rr_i)
INSN(preld, hint_r_i)
INSN(preldx, hint_rr)
INSN(fld_s, fr_i)
INSN(fst_s, fr_i)
INSN(fld_d, fr_i)

5
target/loongarch/insn_trans/trans_memory.c.inc
View file

@ -110,6 +110,11 @@ static bool trans_preld(DisasContext *ctx, arg_preld *a)
return true;
}
static bool trans_preldx(DisasContext *ctx, arg_preldx * a)
{
return true;
}
static bool trans_dbar(DisasContext *ctx, arg_dbar * a)
{
tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);

3
target/loongarch/insns.decode
View file

@ -24,6 +24,7 @@
&rrr rd rj rk
&rr_i rd rj imm
&hint_r_i hint rj imm
&hint_rr hint rj rk
&rrr_sa rd rj rk sa
&rr_ms_ls rd rj ms ls
&ff fd fj
@ -69,6 +70,7 @@
@rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i
@rr_i16s2 .... .. ................ rj:5 rd:5 &rr_i imm=%offs16
@hint_r_i12 .... ...... imm:s12 rj:5 hint:5 &hint_r_i
@hint_rr .... ........ ..... rk:5 rj:5 hint:5 &hint_rr
@rrr_sa2p1 .... ........ ... .. rk:5 rj:5 rd:5 &rrr_sa sa=%sa2p1
@rrr_sa2 .... ........ ... sa:2 rk:5 rj:5 rd:5 &rrr_sa
@rrr_sa3 .... ........ .. sa:3 rk:5 rj:5 rd:5 &rrr_sa
@ -228,6 +230,7 @@ ldx_bu 0011 10000010 00000 ..... ..... ..... @rrr
ldx_hu 0011 10000010 01000 ..... ..... ..... @rrr
ldx_wu 0011 10000010 10000 ..... ..... ..... @rrr
preld 0010 101011 ............ ..... ..... @hint_r_i12
preldx 0011 10000010 11000 ..... ..... ..... @hint_rr
dbar 0011 10000111 00100 ............... @i15
ibar 0011 10000111 00101 ............... @i15
ldptr_w 0010 0100 .............. ..... ..... @rr_i14s2