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tcg: Convert muluh to TCGOutOpBinary

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Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-07 10:16:03 -08:00
parent d2c3ecadea
commit 937246f2ee
23 changed files with 123 additions and 82 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tcg/aarch64/tcg-target-has.h
View file

@ -27,7 +27,6 @@
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_mulu2_i32 0
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
@ -47,7 +46,6 @@
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_muluh_i64 1
#define TCG_TARGET_HAS_mulsh_i64 1
/*

21
tcg/aarch64/tcg-target.c.inc
View file

@ -2179,6 +2179,23 @@ static const TCGOutOpBinary outop_mul = {
.out_rrr = tgen_mul,
};
static TCGConstraintSetIndex cset_mulh(TCGType type, unsigned flags)
{
return type == TCG_TYPE_I64 ? C_O1_I2(r, r, r) : C_NotImplemented;
}
static void tgen_muluh(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_insn(s, 3508, UMULH, TCG_TYPE_I64, a0, a1, a2);
}
static const TCGOutOpBinary outop_muluh = {
.base.static_constraint = C_Dynamic,
.base.dynamic_constraint = cset_mulh,
.out_rrr = tgen_muluh,
};
static const TCGOutOpBinary outop_nand = {
.base.static_constraint = C_NotImplemented,
};
@ -2526,9 +2543,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
args[5], const_args[4], const_args[5], true);
break;
case INDEX_op_muluh_i64:
tcg_out_insn(s, 3508, UMULH, TCG_TYPE_I64, a0, a1, a2);
break;
case INDEX_op_mulsh_i64:
tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2);
break;
@ -3043,7 +3057,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_rem_i64:
case INDEX_op_remu_i32:
case INDEX_op_remu_i64:
case INDEX_op_muluh_i64:
case INDEX_op_mulsh_i64:
return C_O1_I2(r, r, r);

1
tcg/arm/tcg-target-has.h
View file

@ -34,7 +34,6 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_negsetcond_i32 1
#define TCG_TARGET_HAS_mulu2_i32 1
#define TCG_TARGET_HAS_muls2_i32 1
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_div_i32 use_idiv_instructions
#define TCG_TARGET_HAS_rem_i32 0

4
tcg/arm/tcg-target.c.inc
View file

@ -1890,6 +1890,10 @@ static const TCGOutOpBinary outop_mul = {
.out_rrr = tgen_mul,
};
static const TCGOutOpBinary outop_muluh = {
.base.static_constraint = C_NotImplemented,
};
static const TCGOutOpBinary outop_nand = {
.base.static_constraint = C_NotImplemented,
};

2
tcg/i386/tcg-target-has.h
View file

@ -39,7 +39,6 @@
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_mulu2_i32 1
#define TCG_TARGET_HAS_muls2_i32 1
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
#if TCG_TARGET_REG_BITS == 64
@ -59,7 +58,6 @@
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 1
#define TCG_TARGET_HAS_muls2_i64 1
#define TCG_TARGET_HAS_muluh_i64 0
#define TCG_TARGET_HAS_mulsh_i64 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
#else

4
tcg/i386/tcg-target.c.inc
View file

@ -2664,6 +2664,10 @@ static const TCGOutOpBinary outop_mul = {
.out_rri = tgen_muli,
};
static const TCGOutOpBinary outop_muluh = {
.base.static_constraint = C_NotImplemented,
};
static const TCGOutOpBinary outop_nand = {
.base.static_constraint = C_NotImplemented,
};

2
tcg/loongarch64/tcg-target-has.h
View file

@ -20,7 +20,6 @@
#define TCG_TARGET_HAS_sub2_i32 0
#define TCG_TARGET_HAS_mulu2_i32 0
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_muluh_i32 1
#define TCG_TARGET_HAS_mulsh_i32 1
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
@ -47,7 +46,6 @@
#define TCG_TARGET_HAS_sub2_i64 0
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_muluh_i64 1
#define TCG_TARGET_HAS_mulsh_i64 1
#define TCG_TARGET_HAS_qemu_ldst_i128 (cpuinfo & CPUINFO_LSX)

24
tcg/loongarch64/tcg-target.c.inc
View file

@ -1347,6 +1347,21 @@ static const TCGOutOpBinary outop_mul = {
.out_rrr = tgen_mul,
};
static void tgen_muluh(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
if (type == TCG_TYPE_I32) {
tcg_out_opc_mulh_wu(s, a0, a1, a2);
} else {
tcg_out_opc_mulh_du(s, a0, a1, a2);
}
}
static const TCGOutOpBinary outop_muluh = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_muluh,
};
static const TCGOutOpBinary outop_nand = {
.base.static_constraint = C_NotImplemented,
};
@ -1648,13 +1663,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_opc_mulh_d(s, a0, a1, a2);
break;
case INDEX_op_muluh_i32:
tcg_out_opc_mulh_wu(s, a0, a1, a2);
break;
case INDEX_op_muluh_i64:
tcg_out_opc_mulh_du(s, a0, a1, a2);
break;
case INDEX_op_div_i32:
tcg_out_opc_div_w(s, a0, a1, a2);
break;
@ -2343,8 +2351,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_mulsh_i32:
case INDEX_op_mulsh_i64:
case INDEX_op_muluh_i32:
case INDEX_op_muluh_i64:
case INDEX_op_div_i32:
case INDEX_op_div_i64:
case INDEX_op_divu_i32:

2
tcg/mips/tcg-target-has.h
View file

@ -43,7 +43,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_rem_i32 1
#define TCG_TARGET_HAS_mulu2_i32 (!use_mips32r6_instructions)
#define TCG_TARGET_HAS_muls2_i32 (!use_mips32r6_instructions)
#define TCG_TARGET_HAS_muluh_i32 1
#define TCG_TARGET_HAS_mulsh_i32 1
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
@ -59,7 +58,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_sub2_i64 0
#define TCG_TARGET_HAS_mulu2_i64 (!use_mips32r6_instructions)
#define TCG_TARGET_HAS_muls2_i64 (!use_mips32r6_instructions)
#define TCG_TARGET_HAS_muluh_i64 1
#define TCG_TARGET_HAS_mulsh_i64 1
#define TCG_TARGET_HAS_ext32s_i64 1
#define TCG_TARGET_HAS_ext32u_i64 1

34
tcg/mips/tcg-target.c.inc
View file

@ -1743,6 +1743,24 @@ static const TCGOutOpBinary outop_mul = {
.out_rrr = tgen_mul,
};
static void tgen_muluh(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
if (use_mips32r6_instructions) {
MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MUHU : OPC_DMUHU;
tcg_out_opc_reg(s, insn, a0, a1, a2);
} else {
MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULTU : OPC_DMULTU;
tcg_out_opc_reg(s, insn, 0, a1, a2);
tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0);
}
}
static const TCGOutOpBinary outop_muluh = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_muluh,
};
static const TCGOutOpBinary outop_nand = {
.base.static_constraint = C_NotImplemented,
};
@ -1910,13 +1928,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
i1 = OPC_MULT, i2 = OPC_MFHI;
goto do_hilo1;
case INDEX_op_muluh_i32:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2);
break;
}
i1 = OPC_MULTU, i2 = OPC_MFHI;
goto do_hilo1;
case INDEX_op_div_i32:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2);
@ -1952,13 +1963,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
i1 = OPC_DMULT, i2 = OPC_MFHI;
goto do_hilo1;
case INDEX_op_muluh_i64:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2);
break;
}
i1 = OPC_DMULTU, i2 = OPC_MFHI;
goto do_hilo1;
case INDEX_op_div_i64:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
@ -2246,14 +2250,12 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
return C_O0_I2(rz, r);
case INDEX_op_mulsh_i32:
case INDEX_op_muluh_i32:
case INDEX_op_div_i32:
case INDEX_op_divu_i32:
case INDEX_op_rem_i32:
case INDEX_op_remu_i32:
case INDEX_op_setcond_i32:
case INDEX_op_mulsh_i64:
case INDEX_op_muluh_i64:
case INDEX_op_div_i64:
case INDEX_op_divu_i64:
case INDEX_op_rem_i64:

2
tcg/ppc/tcg-target-has.h
View file

@ -29,7 +29,6 @@
#define TCG_TARGET_HAS_negsetcond_i32 1
#define TCG_TARGET_HAS_mulu2_i32 0
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_muluh_i32 1
#define TCG_TARGET_HAS_mulsh_i32 1
#define TCG_TARGET_HAS_qemu_st8_i32 0
@ -52,7 +51,6 @@
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_muluh_i64 1
#define TCG_TARGET_HAS_mulsh_i64 1
#endif

20
tcg/ppc/tcg-target.c.inc
View file

@ -2984,6 +2984,18 @@ static const TCGOutOpBinary outop_mul = {
.out_rri = tgen_muli,
};
static void tgen_muluh(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
uint32_t insn = type == TCG_TYPE_I32 ? MULHWU : MULHDU;
tcg_out32(s, insn | TAB(a0, a1, a2));
}
static const TCGOutOpBinary outop_muluh = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_muluh,
};
static void tgen_nand(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
@ -3487,15 +3499,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
break;
case INDEX_op_muluh_i32:
tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2]));
break;
case INDEX_op_mulsh_i32:
tcg_out32(s, MULHW | TAB(args[0], args[1], args[2]));
break;
case INDEX_op_muluh_i64:
tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
break;
case INDEX_op_mulsh_i64:
tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
break;
@ -4177,14 +4183,12 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_divu_i32:
case INDEX_op_rem_i32:
case INDEX_op_remu_i32:
case INDEX_op_muluh_i32:
case INDEX_op_mulsh_i32:
case INDEX_op_div_i64:
case INDEX_op_divu_i64:
case INDEX_op_rem_i64:
case INDEX_op_remu_i64:
case INDEX_op_mulsh_i64:
case INDEX_op_muluh_i64:
return C_O1_I2(r, r, r);
case INDEX_op_clz_i32:

2
tcg/riscv/tcg-target-has.h
View file

@ -20,7 +20,6 @@
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_mulu2_i32 0
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB)
@ -46,7 +45,6 @@
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_muluh_i64 1
#define TCG_TARGET_HAS_mulsh_i64 1
#define TCG_TARGET_HAS_qemu_ldst_i128 0

24
tcg/riscv/tcg-target.c.inc
View file

@ -2021,6 +2021,23 @@ static const TCGOutOpBinary outop_mul = {
.out_rrr = tgen_mul,
};
static TCGConstraintSetIndex cset_mulh(TCGType type, unsigned flags)
{
return type == TCG_TYPE_I32 ? C_NotImplemented : C_O1_I2(r, r, r);
}
static void tgen_muluh(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_opc_reg(s, OPC_MULHU, a0, a1, a2);
}
static const TCGOutOpBinary outop_muluh = {
.base.static_constraint = C_Dynamic,
.base.dynamic_constraint = cset_mulh,
.out_rrr = tgen_muluh,
};
static const TCGOutOpBinary outop_nand = {
.base.static_constraint = C_NotImplemented,
};
@ -2379,11 +2396,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2);
break;
case INDEX_op_muluh_i32:
case INDEX_op_muluh_i64:
tcg_out_opc_reg(s, OPC_MULHU, a0, a1, a2);
break;
case INDEX_op_mb:
tcg_out_mb(s, a0);
break;
@ -2712,13 +2724,11 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
return C_O1_I2(r, r, rI);
case INDEX_op_mulsh_i32:
case INDEX_op_muluh_i32:
case INDEX_op_div_i32:
case INDEX_op_divu_i32:
case INDEX_op_rem_i32:
case INDEX_op_remu_i32:
case INDEX_op_mulsh_i64:
case INDEX_op_muluh_i64:
case INDEX_op_div_i64:
case INDEX_op_divu_i64:
case INDEX_op_rem_i64:

2
tcg/s390x/tcg-target-has.h
View file

@ -42,7 +42,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_mulu2_i32 0
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
@ -61,7 +60,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 1
#define TCG_TARGET_HAS_muls2_i64 HAVE_FACILITY(MISC_INSN_EXT2)
#define TCG_TARGET_HAS_muluh_i64 0
#define TCG_TARGET_HAS_mulsh_i64 0
#define TCG_TARGET_HAS_qemu_ldst_i128 1

4
tcg/s390x/tcg-target.c.inc
View file

@ -2309,6 +2309,10 @@ static const TCGOutOpBinary outop_mul = {
.out_rri = tgen_muli,
};
static const TCGOutOpBinary outop_muluh = {
.base.static_constraint = C_NotImplemented,
};
static void tgen_nand(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{

2
tcg/sparc64/tcg-target-has.h
View file

@ -28,7 +28,6 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_mulu2_i32 1
#define TCG_TARGET_HAS_muls2_i32 1
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
@ -48,7 +47,6 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_muluh_i64 use_vis3_instructions
#define TCG_TARGET_HAS_mulsh_i64 0
#define TCG_TARGET_HAS_qemu_ldst_i128 0

23
tcg/sparc64/tcg-target.c.inc
View file

@ -1357,6 +1357,24 @@ static const TCGOutOpBinary outop_mul = {
.out_rri = tgen_muli,
};
static void tgen_muluh(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_arith(s, a0, a1, a2, ARITH_UMULXHI);
}
static TCGConstraintSetIndex cset_muluh(TCGType type, unsigned flags)
{
return (type == TCG_TYPE_I64 && use_vis3_instructions
? C_O1_I2(r, r, r) : C_NotImplemented);
}
static const TCGOutOpBinary outop_muluh = {
.base.static_constraint = C_Dynamic,
.base.dynamic_constraint = cset_muluh,
.out_rrr = tgen_muluh,
};
static const TCGOutOpBinary outop_nand = {
.base.static_constraint = C_NotImplemented,
};
@ -1612,9 +1630,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4],
const_args[4], args[5], const_args[5], true);
break;
case INDEX_op_muluh_i64:
tcg_out_arith(s, args[0], args[1], args[2], ARITH_UMULXHI);
break;
gen_arith:
tcg_out_arithc(s, a0, a1, a2, c2, c);
@ -1711,8 +1726,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_mulu2_i32:
case INDEX_op_muls2_i32:
return C_O2_I2(r, r, rz, rJ);
case INDEX_op_muluh_i64:
return C_O1_I2(r, r, r);
default:
return C_NotImplemented;

1
tcg/tcg-has.h
View file

@ -28,7 +28,6 @@
#define TCG_TARGET_HAS_sub2_i64 0
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_muluh_i64 0
#define TCG_TARGET_HAS_mulsh_i64 0
/* Turn some undef macros into true macros. */
#define TCG_TARGET_HAS_add2_i32 1

7
tcg/tcg-op.c
View file

@ -1132,7 +1132,7 @@ void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2)
{
if (TCG_TARGET_HAS_mulu2_i32) {
tcg_gen_op4_i32(INDEX_op_mulu2_i32, rl, rh, arg1, arg2);
} else if (TCG_TARGET_HAS_muluh_i32) {
} else if (tcg_op_supported(INDEX_op_muluh_i32, TCG_TYPE_I32, 0)) {
TCGv_i32 t = tcg_temp_ebb_new_i32();
tcg_gen_op3_i32(INDEX_op_mul, t, arg1, arg2);
tcg_gen_op3_i32(INDEX_op_muluh_i32, rh, arg1, arg2);
@ -2842,7 +2842,7 @@ void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2)
{
if (TCG_TARGET_HAS_mulu2_i64) {
tcg_gen_op4_i64(INDEX_op_mulu2_i64, rl, rh, arg1, arg2);
} else if (TCG_TARGET_HAS_muluh_i64) {
} else if (tcg_op_supported(INDEX_op_muluh_i64, TCG_TYPE_I64, 0)) {
TCGv_i64 t = tcg_temp_ebb_new_i64();
tcg_gen_op3_i64(INDEX_op_mul, t, arg1, arg2);
tcg_gen_op3_i64(INDEX_op_muluh_i64, rh, arg1, arg2);
@ -2867,7 +2867,8 @@ void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2)
tcg_gen_op3_i64(INDEX_op_mulsh_i64, rh, arg1, arg2);
tcg_gen_mov_i64(rl, t);
tcg_temp_free_i64(t);
} else if (TCG_TARGET_HAS_mulu2_i64 || TCG_TARGET_HAS_muluh_i64) {
} else if (TCG_TARGET_HAS_mulu2_i64 ||
tcg_op_supported(INDEX_op_muluh_i64, TCG_TYPE_I64, 0)) {
TCGv_i64 t0 = tcg_temp_ebb_new_i64();
TCGv_i64 t1 = tcg_temp_ebb_new_i64();
TCGv_i64 t2 = tcg_temp_ebb_new_i64();

16
tcg/tcg.c
View file

@ -1022,6 +1022,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv),
OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul),
OUTOP(INDEX_op_muluh_i32, TCGOutOpBinary, outop_muluh),
OUTOP(INDEX_op_muluh_i64, TCGOutOpBinary, outop_muluh),
OUTOP(INDEX_op_nand, TCGOutOpBinary, outop_nand),
OUTOP(INDEX_op_neg, TCGOutOpUnary, outop_neg),
OUTOP(INDEX_op_nor, TCGOutOpBinary, outop_nor),
@ -2280,8 +2282,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
return TCG_TARGET_HAS_mulu2_i32;
case INDEX_op_muls2_i32:
return TCG_TARGET_HAS_muls2_i32;
case INDEX_op_muluh_i32:
return TCG_TARGET_HAS_muluh_i32;
case INDEX_op_mulsh_i32:
return TCG_TARGET_HAS_mulsh_i32;
case INDEX_op_bswap16_i32:
@ -2362,8 +2362,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
return TCG_TARGET_HAS_mulu2_i64;
case INDEX_op_muls2_i64:
return TCG_TARGET_HAS_muls2_i64;
case INDEX_op_muluh_i64:
return TCG_TARGET_HAS_muluh_i64;
case INDEX_op_mulsh_i64:
return TCG_TARGET_HAS_mulsh_i64;
@ -3876,7 +3874,6 @@ liveness_pass_1(TCGContext *s)
QTAILQ_FOREACH_REVERSE_SAFE(op, &s->ops, link, op_prev) {
int nb_iargs, nb_oargs;
TCGOpcode opc_new, opc_new2;
bool have_opc_new2;
TCGLifeData arg_life = 0;
TCGTemp *ts;
TCGOpcode opc = op->opc;
@ -4036,22 +4033,18 @@ liveness_pass_1(TCGContext *s)
case INDEX_op_mulu2_i32:
opc_new = INDEX_op_mul;
opc_new2 = INDEX_op_muluh_i32;
have_opc_new2 = TCG_TARGET_HAS_muluh_i32;
goto do_mul2;
case INDEX_op_muls2_i32:
opc_new = INDEX_op_mul;
opc_new2 = INDEX_op_mulsh_i32;
have_opc_new2 = TCG_TARGET_HAS_mulsh_i32;
goto do_mul2;
case INDEX_op_mulu2_i64:
opc_new = INDEX_op_mul;
opc_new2 = INDEX_op_muluh_i64;
have_opc_new2 = TCG_TARGET_HAS_muluh_i64;
goto do_mul2;
case INDEX_op_muls2_i64:
opc_new = INDEX_op_mul;
opc_new2 = INDEX_op_mulsh_i64;
have_opc_new2 = TCG_TARGET_HAS_mulsh_i64;
goto do_mul2;
do_mul2:
nb_iargs = 2;
@ -4065,7 +4058,8 @@ liveness_pass_1(TCGContext *s)
op->opc = opc = opc_new;
op->args[1] = op->args[2];
op->args[2] = op->args[3];
} else if (arg_temp(op->args[0])->state == TS_DEAD && have_opc_new2) {
} else if (arg_temp(op->args[0])->state == TS_DEAD &&
tcg_op_supported(opc_new2, TCGOP_TYPE(op), 0)) {
/* The low part of the operation is dead; generate the high. */
op->opc = opc = opc_new2;
op->args[0] = op->args[1];
@ -5436,6 +5430,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
case INDEX_op_andc:
case INDEX_op_eqv:
case INDEX_op_mul:
case INDEX_op_muluh_i32:
case INDEX_op_muluh_i64:
case INDEX_op_nand:
case INDEX_op_nor:
case INDEX_op_or:

2
tcg/tci/tcg-target-has.h
View file

@ -18,7 +18,6 @@
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_negsetcond_i32 0
#define TCG_TARGET_HAS_muls2_i32 1
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
@ -42,7 +41,6 @@
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 1
#define TCG_TARGET_HAS_muluh_i64 0
#define TCG_TARGET_HAS_mulsh_i64 0
#else
#define TCG_TARGET_HAS_mulu2_i32 1

4
tcg/tci/tcg-target.c.inc
View file

@ -670,6 +670,10 @@ static const TCGOutOpBinary outop_mul = {
.out_rrr = tgen_mul,
};
static const TCGOutOpBinary outop_muluh = {
.base.static_constraint = C_NotImplemented,
};
static void tgen_nand(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{