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target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA

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Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Bastian Koppelmann 2015-05-11 14:59:55 +02:00
parent 0e045f43c4
commit 9371557115
4 changed files with 74 additions and 0 deletions
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2
target-tricore/tricore-opcodes.h
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@ -1124,6 +1124,8 @@ enum {
OPC2_32_RR_PARITY = 0x02,
OPC2_32_RR_UNPACK = 0x08,
OPC2_32_RR_CRC32 = 0x03,
OPC2_32_RR_DIV = 0x20,
OPC2_32_RR_DIV_U = 0x21,
};
/* OPCM_32_RR_IDIRECT */
enum {