mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-03 07:43:54 -06:00
Rename CPUState -> CPUArchState
Scripted conversion:
for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do
sed -i "s/CPUState/CPUArchState/g" $file
done
All occurrences of CPUArchState are expected to be replaced by QOM CPUState,
once all targets are QOM'ified and common fields have been extracted.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Andreas Färber
parent
5bfcb36ec4
commit
9349b4f9fd
59 changed files with 419 additions and 419 deletions
114
exec.c
114
exec.c
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@ -123,10 +123,10 @@ static MemoryRegion io_mem_subpage_ram;
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#endif
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CPUState *first_cpu;
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CPUArchState *first_cpu;
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/* current CPU in the current thread. It is only valid inside
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cpu_exec() */
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DEFINE_TLS(CPUState *,cpu_single_env);
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DEFINE_TLS(CPUArchState *,cpu_single_env);
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/* 0 = Do not count executed instructions.
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1 = Precise instruction counting.
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2 = Adaptive rate instruction counting. */
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@ -509,7 +509,7 @@ static target_phys_addr_t section_addr(MemoryRegionSection *section,
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}
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static void tlb_protect_code(ram_addr_t ram_addr);
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static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
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static void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
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target_ulong vaddr);
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#define mmap_lock() do { } while(0)
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#define mmap_unlock() do { } while(0)
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@ -661,7 +661,7 @@ void cpu_exec_init_all(void)
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static int cpu_common_post_load(void *opaque, int version_id)
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{
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CPUState *env = opaque;
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CPUArchState *env = opaque;
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/* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
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version_id is increased. */
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@ -678,16 +678,16 @@ static const VMStateDescription vmstate_cpu_common = {
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.minimum_version_id_old = 1,
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.post_load = cpu_common_post_load,
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.fields = (VMStateField []) {
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VMSTATE_UINT32(halted, CPUState),
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VMSTATE_UINT32(interrupt_request, CPUState),
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VMSTATE_UINT32(halted, CPUArchState),
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VMSTATE_UINT32(interrupt_request, CPUArchState),
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VMSTATE_END_OF_LIST()
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}
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};
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#endif
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CPUState *qemu_get_cpu(int cpu)
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CPUArchState *qemu_get_cpu(int cpu)
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{
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CPUState *env = first_cpu;
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CPUArchState *env = first_cpu;
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while (env) {
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if (env->cpu_index == cpu)
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@ -698,9 +698,9 @@ CPUState *qemu_get_cpu(int cpu)
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return env;
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}
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void cpu_exec_init(CPUState *env)
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void cpu_exec_init(CPUArchState *env)
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{
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CPUState **penv;
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CPUArchState **penv;
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int cpu_index;
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#if defined(CONFIG_USER_ONLY)
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@ -799,9 +799,9 @@ static void page_flush_tb(void)
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/* flush all the translation blocks */
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/* XXX: tb_flush is currently not thread safe */
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void tb_flush(CPUState *env1)
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void tb_flush(CPUArchState *env1)
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{
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CPUState *env;
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CPUArchState *env;
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#if defined(DEBUG_FLUSH)
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printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
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(unsigned long)(code_gen_ptr - code_gen_buffer),
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@ -934,7 +934,7 @@ static inline void tb_reset_jump(TranslationBlock *tb, int n)
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void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
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{
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CPUState *env;
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CPUArchState *env;
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PageDesc *p;
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unsigned int h, n1;
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tb_page_addr_t phys_pc;
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@ -1043,7 +1043,7 @@ static void build_page_bitmap(PageDesc *p)
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}
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}
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TranslationBlock *tb_gen_code(CPUState *env,
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TranslationBlock *tb_gen_code(CPUArchState *env,
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target_ulong pc, target_ulong cs_base,
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int flags, int cflags)
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{
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@ -1090,7 +1090,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
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int is_cpu_write_access)
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{
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TranslationBlock *tb, *tb_next, *saved_tb;
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CPUState *env = cpu_single_env;
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CPUArchState *env = cpu_single_env;
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tb_page_addr_t tb_start, tb_end;
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PageDesc *p;
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int n;
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@ -1227,7 +1227,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr,
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int n;
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#ifdef TARGET_HAS_PRECISE_SMC
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TranslationBlock *current_tb = NULL;
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CPUState *env = cpu_single_env;
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CPUArchState *env = cpu_single_env;
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int current_tb_modified = 0;
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target_ulong current_pc = 0;
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target_ulong current_cs_base = 0;
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@ -1457,12 +1457,12 @@ static void tb_reset_jump_recursive(TranslationBlock *tb)
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#if defined(TARGET_HAS_ICE)
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#if defined(CONFIG_USER_ONLY)
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static void breakpoint_invalidate(CPUState *env, target_ulong pc)
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static void breakpoint_invalidate(CPUArchState *env, target_ulong pc)
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{
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tb_invalidate_phys_page_range(pc, pc + 1, 0);
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}
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#else
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static void breakpoint_invalidate(CPUState *env, target_ulong pc)
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static void breakpoint_invalidate(CPUArchState *env, target_ulong pc)
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{
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target_phys_addr_t addr;
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ram_addr_t ram_addr;
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@ -1482,19 +1482,19 @@ static void breakpoint_invalidate(CPUState *env, target_ulong pc)
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#endif /* TARGET_HAS_ICE */
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#if defined(CONFIG_USER_ONLY)
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void cpu_watchpoint_remove_all(CPUState *env, int mask)
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void cpu_watchpoint_remove_all(CPUArchState *env, int mask)
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{
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}
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int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
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int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
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int flags, CPUWatchpoint **watchpoint)
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{
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return -ENOSYS;
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}
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#else
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/* Add a watchpoint. */
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int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
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int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
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int flags, CPUWatchpoint **watchpoint)
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{
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target_ulong len_mask = ~(len - 1);
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@ -1527,7 +1527,7 @@ int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
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}
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/* Remove a specific watchpoint. */
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int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len,
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int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len,
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int flags)
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{
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target_ulong len_mask = ~(len - 1);
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@ -1544,7 +1544,7 @@ int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len,
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}
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/* Remove a specific watchpoint by reference. */
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void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint)
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void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint)
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{
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QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry);
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@ -1554,7 +1554,7 @@ void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint)
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}
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/* Remove all matching watchpoints. */
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void cpu_watchpoint_remove_all(CPUState *env, int mask)
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void cpu_watchpoint_remove_all(CPUArchState *env, int mask)
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{
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CPUWatchpoint *wp, *next;
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@ -1566,7 +1566,7 @@ void cpu_watchpoint_remove_all(CPUState *env, int mask)
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#endif
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/* Add a breakpoint. */
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int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
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int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
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CPUBreakpoint **breakpoint)
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{
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#if defined(TARGET_HAS_ICE)
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@ -1594,7 +1594,7 @@ int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
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}
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/* Remove a specific breakpoint. */
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int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags)
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int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags)
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{
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#if defined(TARGET_HAS_ICE)
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CPUBreakpoint *bp;
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@ -1612,7 +1612,7 @@ int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags)
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}
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/* Remove a specific breakpoint by reference. */
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void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint)
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void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint)
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{
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#if defined(TARGET_HAS_ICE)
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QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry);
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@ -1624,7 +1624,7 @@ void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint)
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}
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/* Remove all matching breakpoints. */
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void cpu_breakpoint_remove_all(CPUState *env, int mask)
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void cpu_breakpoint_remove_all(CPUArchState *env, int mask)
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{
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#if defined(TARGET_HAS_ICE)
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CPUBreakpoint *bp, *next;
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@ -1638,7 +1638,7 @@ void cpu_breakpoint_remove_all(CPUState *env, int mask)
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/* enable or disable single step mode. EXCP_DEBUG is returned by the
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CPU loop after each instruction */
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void cpu_single_step(CPUState *env, int enabled)
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void cpu_single_step(CPUArchState *env, int enabled)
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{
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#if defined(TARGET_HAS_ICE)
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if (env->singlestep_enabled != enabled) {
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@ -1694,7 +1694,7 @@ void cpu_set_log_filename(const char *filename)
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cpu_set_log(loglevel);
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}
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static void cpu_unlink_tb(CPUState *env)
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static void cpu_unlink_tb(CPUArchState *env)
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{
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/* FIXME: TB unchaining isn't SMP safe. For now just ignore the
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problem and hope the cpu will stop of its own accord. For userspace
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@ -1716,7 +1716,7 @@ static void cpu_unlink_tb(CPUState *env)
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#ifndef CONFIG_USER_ONLY
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/* mask must never be zero, except for A20 change call */
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static void tcg_handle_interrupt(CPUState *env, int mask)
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static void tcg_handle_interrupt(CPUArchState *env, int mask)
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{
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int old_mask;
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@ -1747,19 +1747,19 @@ CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt;
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#else /* CONFIG_USER_ONLY */
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void cpu_interrupt(CPUState *env, int mask)
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void cpu_interrupt(CPUArchState *env, int mask)
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{
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env->interrupt_request |= mask;
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cpu_unlink_tb(env);
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}
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#endif /* CONFIG_USER_ONLY */
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void cpu_reset_interrupt(CPUState *env, int mask)
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void cpu_reset_interrupt(CPUArchState *env, int mask)
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{
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env->interrupt_request &= ~mask;
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}
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void cpu_exit(CPUState *env)
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void cpu_exit(CPUArchState *env)
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{
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env->exit_request = 1;
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cpu_unlink_tb(env);
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@ -1837,7 +1837,7 @@ int cpu_str_to_log_mask(const char *str)
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return mask;
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}
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void cpu_abort(CPUState *env, const char *fmt, ...)
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void cpu_abort(CPUArchState *env, const char *fmt, ...)
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{
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va_list ap;
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va_list ap2;
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@ -1877,17 +1877,17 @@ void cpu_abort(CPUState *env, const char *fmt, ...)
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abort();
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}
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CPUState *cpu_copy(CPUState *env)
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CPUArchState *cpu_copy(CPUArchState *env)
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{
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CPUState *new_env = cpu_init(env->cpu_model_str);
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CPUState *next_cpu = new_env->next_cpu;
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CPUArchState *new_env = cpu_init(env->cpu_model_str);
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CPUArchState *next_cpu = new_env->next_cpu;
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int cpu_index = new_env->cpu_index;
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#if defined(TARGET_HAS_ICE)
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CPUBreakpoint *bp;
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CPUWatchpoint *wp;
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#endif
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memcpy(new_env, env, sizeof(CPUState));
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memcpy(new_env, env, sizeof(CPUArchState));
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/* Preserve chaining and index. */
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new_env->next_cpu = next_cpu;
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@ -1913,7 +1913,7 @@ CPUState *cpu_copy(CPUState *env)
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#if !defined(CONFIG_USER_ONLY)
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static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
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static inline void tlb_flush_jmp_cache(CPUArchState *env, target_ulong addr)
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{
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unsigned int i;
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@ -1947,7 +1947,7 @@ static CPUTLBEntry s_cputlb_empty_entry = {
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* entries from the TLB at any time, so flushing more entries than
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* required is only an efficiency issue, not a correctness issue.
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*/
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void tlb_flush(CPUState *env, int flush_global)
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void tlb_flush(CPUArchState *env, int flush_global)
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{
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int i;
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@ -1984,7 +1984,7 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
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}
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}
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void tlb_flush_page(CPUState *env, target_ulong addr)
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void tlb_flush_page(CPUArchState *env, target_ulong addr)
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{
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int i;
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int mmu_idx;
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@ -2025,7 +2025,7 @@ static void tlb_protect_code(ram_addr_t ram_addr)
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/* update the TLB so that writes in physical page 'phys_addr' are no longer
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tested for self modifying code */
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static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
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static void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
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target_ulong vaddr)
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{
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cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG);
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@ -2047,7 +2047,7 @@ static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
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void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
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int dirty_flags)
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{
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CPUState *env;
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CPUArchState *env;
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unsigned long length, start1;
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int i;
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@ -2102,7 +2102,7 @@ static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
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}
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/* update the TLB according to the current state of the dirty bits */
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void cpu_tlb_update_dirty(CPUState *env)
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void cpu_tlb_update_dirty(CPUArchState *env)
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{
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int i;
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int mmu_idx;
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@ -2120,7 +2120,7 @@ static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
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/* update the TLB corresponding to virtual page vaddr
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so that it is no longer dirty */
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static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
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static inline void tlb_set_dirty(CPUArchState *env, target_ulong vaddr)
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{
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int i;
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int mmu_idx;
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@ -2133,7 +2133,7 @@ static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
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/* Our TLB does not support large pages, so remember the area covered by
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large pages and trigger a full TLB flush if these are invalidated. */
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static void tlb_add_large_page(CPUState *env, target_ulong vaddr,
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static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
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target_ulong size)
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{
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target_ulong mask = ~(size - 1);
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@ -2174,7 +2174,7 @@ static bool is_ram_rom_romd(MemoryRegionSection *s)
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/* Add a new TLB entry. At most one entry for a given virtual address
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is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
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supplied size is only used by tlb_flush_page. */
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void tlb_set_page(CPUState *env, target_ulong vaddr,
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void tlb_set_page(CPUArchState *env, target_ulong vaddr,
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target_phys_addr_t paddr, int prot,
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int mmu_idx, target_ulong size)
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{
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@ -2277,11 +2277,11 @@ void tlb_set_page(CPUState *env, target_ulong vaddr,
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#else
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void tlb_flush(CPUState *env, int flush_global)
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void tlb_flush(CPUArchState *env, int flush_global)
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{
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}
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void tlb_flush_page(CPUState *env, target_ulong addr)
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void tlb_flush_page(CPUArchState *env, target_ulong addr)
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{
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}
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@ -2542,7 +2542,7 @@ int page_unprotect(target_ulong address, unsigned long pc, void *puc)
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return 0;
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}
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static inline void tlb_set_dirty(CPUState *env,
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static inline void tlb_set_dirty(CPUArchState *env,
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unsigned long addr, target_ulong vaddr)
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{
|
||||
}
|
||||
|
|
@ -3299,7 +3299,7 @@ static const MemoryRegionOps notdirty_mem_ops = {
|
|||
/* Generate a debug exception if a watchpoint has been hit. */
|
||||
static void check_watchpoint(int offset, int len_mask, int flags)
|
||||
{
|
||||
CPUState *env = cpu_single_env;
|
||||
CPUArchState *env = cpu_single_env;
|
||||
target_ulong pc, cs_base;
|
||||
TranslationBlock *tb;
|
||||
target_ulong vaddr;
|
||||
|
|
@ -3544,7 +3544,7 @@ static void core_begin(MemoryListener *listener)
|
|||
|
||||
static void core_commit(MemoryListener *listener)
|
||||
{
|
||||
CPUState *env;
|
||||
CPUArchState *env;
|
||||
|
||||
/* since each CPU stores ram addresses in its TLB cache, we must
|
||||
reset the modified entries */
|
||||
|
|
@ -3734,7 +3734,7 @@ MemoryRegion *get_system_io(void)
|
|||
|
||||
/* physical memory access (slow version, mainly for debug) */
|
||||
#if defined(CONFIG_USER_ONLY)
|
||||
int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
|
||||
int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
|
||||
uint8_t *buf, int len, int is_write)
|
||||
{
|
||||
int l, flags;
|
||||
|
|
@ -4440,7 +4440,7 @@ void stq_be_phys(target_phys_addr_t addr, uint64_t val)
|
|||
}
|
||||
|
||||
/* virtual memory access for debug (includes writing to ROM) */
|
||||
int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
|
||||
int cpu_memory_rw_debug(CPUArchState *env, target_ulong addr,
|
||||
uint8_t *buf, int len, int is_write)
|
||||
{
|
||||
int l;
|
||||
|
|
@ -4471,7 +4471,7 @@ int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
|
|||
|
||||
/* in deterministic execution mode, instructions doing device I/Os
|
||||
must be at the end of the TB */
|
||||
void cpu_io_recompile(CPUState *env, void *retaddr)
|
||||
void cpu_io_recompile(CPUArchState *env, void *retaddr)
|
||||
{
|
||||
TranslationBlock *tb;
|
||||
uint32_t n, cflags;
|
||||
|
|
@ -4585,7 +4585,7 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fprintf)
|
|||
/* NOTE: this function can trigger an exception */
|
||||
/* NOTE2: the returned address is not exactly the physical address: it
|
||||
is the offset relative to phys_ram_base */
|
||||
tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
|
||||
tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
|
||||
{
|
||||
int mmu_idx, page_index, pd;
|
||||
void *p;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue