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hw/riscv: microchip_pfsoc: Connect DDR memory controller modules

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Connect DDR SGMII PHY module and CFG module to the PolarFire SoC.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-4-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Bin Meng 2020-10-28 13:30:03 +08:00 • committed by Alistair Francis
parent 3400b15bbe
commit 933f73f13e
3 changed files with 24 additions and 0 deletions
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5
include/hw/riscv/microchip_pfsoc.h
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@ -24,6 +24,7 @@
#include "hw/char/mchp_pfsoc_mmuart.h"
#include "hw/dma/sifive_pdma.h"
#include "hw/misc/mchp_pfsoc_dmc.h"
#include "hw/net/cadence_gem.h"
#include "hw/sd/cadence_sdhci.h"
@ -37,6 +38,8 @@ typedef struct MicrochipPFSoCState {
RISCVHartArrayState e_cpus;
RISCVHartArrayState u_cpus;
DeviceState *plic;
MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy;
MchpPfSoCDdrCfgState ddr_cfg;
MchpPfSoCMMUartState *serial0;
MchpPfSoCMMUartState *serial1;
MchpPfSoCMMUartState *serial2;
@ -82,7 +85,9 @@ enum {
MICROCHIP_PFSOC_MMUART0,
MICROCHIP_PFSOC_SYSREG,
MICROCHIP_PFSOC_MPUCFG,
MICROCHIP_PFSOC_DDR_SGMII_PHY,
MICROCHIP_PFSOC_EMMC_SD,
MICROCHIP_PFSOC_DDR_CFG,
MICROCHIP_PFSOC_MMUART1,
MICROCHIP_PFSOC_MMUART2,
MICROCHIP_PFSOC_MMUART3,