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tcg: Remove TCG_OPF_64BIT
This flag is no longer used. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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commit
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2 changed files with 11 additions and 13 deletions
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@ -37,9 +37,9 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
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#define IMPL(X) (__builtin_constant_p(X) && (X) <= 0 ? TCG_OPF_NOT_PRESENT : 0)
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#if TCG_TARGET_REG_BITS == 32
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# define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
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# define IMPL64 TCG_OPF_NOT_PRESENT
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#else
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# define IMPL64 TCG_OPF_64BIT
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# define IMPL64 0
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#endif
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DEF(mb, 0, 0, 1, TCG_OPF_NOT_PRESENT)
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@ -110,7 +110,7 @@ DEF(clz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_clz_i32))
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DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32))
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DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32))
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DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
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DEF(mov_i64, 1, 1, 0, TCG_OPF_NOT_PRESENT)
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DEF(setcond_i64, 1, 2, 1, IMPL64)
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DEF(negsetcond_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_negsetcond_i64))
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DEF(movcond_i64, 1, 4, 1, IMPL64)
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@ -206,18 +206,18 @@ DEF(qemu_ld_a32_i32, 1, 1, 1,
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DEF(qemu_st_a32_i32, 0, 1 + 1, 1,
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_ld_a32_i64, DATA64_ARGS, 1, 1,
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_st_a32_i64, 0, DATA64_ARGS + 1, 1,
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_ld_a64_i32, 1, DATA64_ARGS, 1,
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_st_a64_i32, 0, 1 + DATA64_ARGS, 1,
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_ld_a64_i64, DATA64_ARGS, DATA64_ARGS, 1,
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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DEF(qemu_st_a64_i64, 0, DATA64_ARGS + DATA64_ARGS, 1,
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
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/* Only used by i386 to cope with stupid register constraints. */
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DEF(qemu_st8_a32_i32, 0, 1 + 1, 1,
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@ -229,16 +229,16 @@ DEF(qemu_st8_a64_i32, 0, 1 + DATA64_ARGS, 1,
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/* Only for 64-bit hosts at the moment. */
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DEF(qemu_ld_a32_i128, 2, 1, 1,
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT |
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS |
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IMPL(TCG_TARGET_HAS_qemu_ldst_i128))
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DEF(qemu_ld_a64_i128, 2, 1, 1,
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT |
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS |
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IMPL(TCG_TARGET_HAS_qemu_ldst_i128))
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DEF(qemu_st_a32_i128, 0, 3, 1,
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT |
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS |
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IMPL(TCG_TARGET_HAS_qemu_ldst_i128))
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DEF(qemu_st_a64_i128, 0, 3, 1,
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT |
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TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS |
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IMPL(TCG_TARGET_HAS_qemu_ldst_i128))
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/* Host vector support. */
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@ -699,8 +699,6 @@ enum {
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/* Instruction has side effects: it cannot be removed if its outputs
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are not used, and might trigger exceptions. */
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TCG_OPF_SIDE_EFFECTS = 0x08,
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/* Instruction operands are 64-bits (otherwise 32-bits). */
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TCG_OPF_64BIT = 0x10,
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/* Instruction is optional and not implemented by the host, or insn
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is generic and should not be implemented by the host. */
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TCG_OPF_NOT_PRESENT = 0x20,
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