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RISC-V PR for 9.2
* Fix an access to VXSAT * Expose RV32 cpu to RV64 QEMU * Don't clear PLIC pending bits on IRQ lowering * Make PLIC zeroth priority register read-only * Set vtype.vill on CPU reset * Check and update APLIC pending when write sourcecfg * Avoid dropping charecters with HTIF * Apply FIFO backpressure to guests using SiFive UART * Support for control flow integrity extensions * Support for the IOMMU with the virt machine * set 'aia_mode' to default in error path * clarify how 'riscv-aia' default works -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmci/tQACgkQr3yVEwxT gBNPAQ//dZKjjJm4Sh+UFdUslivBJYtL1rl2UUG2UqiNn/UoYh/vcHoSArljHTjt 8riEStnaQqXziOpMIJjIMLJ4KoiIk2SMvjNfFtcmPiPZEDEpjsTxfUxBFsBee+fI 4KNQKKFeljq4pa+VzVvXEqzCNJIzCThFXTZhZmer00M91HPA8ZQIHpv2JL1sWlgZ /HW24XEDFLGc/JsR55fxpPftlAqP+BfOrqMmbWy7x2Y+G8WI05hM2zTP/W8pnIz3 z0GCRYSBlADtrp+3RqzTwQfK5pXoFc0iDktWVYlhoXaeEmOwo8IYxTjrvBGhnBq+ ySX1DzTa23QmOIxSYYvCRuOxyOK9ziNn+EQ9FiFBt1h1o251CYMil1bwmYXMCMNJ rZwF1HfUx0g2GQW1ZOqh1eeyLO29JiOdV3hxlDO7X4bbISNgU6il5MXmnvf0/XVW Af3YhALeeDbHgHL1iVfjafzaviQc9+YrEX13eX6N2AjcgE5a3F7XNmGfFpFJ+mfQ CPgiwVBXat6UpBUGAt14UM+6wzp+crSgQR5IEGth+mKMKdkWoykvo7A2oHdu39zn 2cdzsshg2qcLLUPTFy06OOTXX382kCWXuykhHOjZ4uu2SJJ7R0W3PlYV8HSde2Vu Rj+89ZlUSICJNXXweQB39r87hNbtRuDIO22V0B9XrApQbJj6/yE= =rPaa -----END PGP SIGNATURE----- Merge tag 'pull-riscv-to-apply-20241031-1' of https://github.com/alistair23/qemu into staging RISC-V PR for 9.2 * Fix an access to VXSAT * Expose RV32 cpu to RV64 QEMU * Don't clear PLIC pending bits on IRQ lowering * Make PLIC zeroth priority register read-only * Set vtype.vill on CPU reset * Check and update APLIC pending when write sourcecfg * Avoid dropping charecters with HTIF * Apply FIFO backpressure to guests using SiFive UART * Support for control flow integrity extensions * Support for the IOMMU with the virt machine * set 'aia_mode' to default in error path * clarify how 'riscv-aia' default works # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmci/tQACgkQr3yVEwxT # gBNPAQ//dZKjjJm4Sh+UFdUslivBJYtL1rl2UUG2UqiNn/UoYh/vcHoSArljHTjt # 8riEStnaQqXziOpMIJjIMLJ4KoiIk2SMvjNfFtcmPiPZEDEpjsTxfUxBFsBee+fI # 4KNQKKFeljq4pa+VzVvXEqzCNJIzCThFXTZhZmer00M91HPA8ZQIHpv2JL1sWlgZ # /HW24XEDFLGc/JsR55fxpPftlAqP+BfOrqMmbWy7x2Y+G8WI05hM2zTP/W8pnIz3 # z0GCRYSBlADtrp+3RqzTwQfK5pXoFc0iDktWVYlhoXaeEmOwo8IYxTjrvBGhnBq+ # ySX1DzTa23QmOIxSYYvCRuOxyOK9ziNn+EQ9FiFBt1h1o251CYMil1bwmYXMCMNJ # rZwF1HfUx0g2GQW1ZOqh1eeyLO29JiOdV3hxlDO7X4bbISNgU6il5MXmnvf0/XVW # Af3YhALeeDbHgHL1iVfjafzaviQc9+YrEX13eX6N2AjcgE5a3F7XNmGfFpFJ+mfQ # CPgiwVBXat6UpBUGAt14UM+6wzp+crSgQR5IEGth+mKMKdkWoykvo7A2oHdu39zn # 2cdzsshg2qcLLUPTFy06OOTXX382kCWXuykhHOjZ4uu2SJJ7R0W3PlYV8HSde2Vu # Rj+89ZlUSICJNXXweQB39r87hNbtRuDIO22V0B9XrApQbJj6/yE= # =rPaa # -----END PGP SIGNATURE----- # gpg: Signature made Thu 31 Oct 2024 03:51:48 GMT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20241031-1' of https://github.com/alistair23/qemu: (50 commits) target/riscv: Fix vcompress with rvv_ta_all_1s target/riscv/kvm: clarify how 'riscv-aia' default works target/riscv/kvm: set 'aia_mode' to default in error path docs/specs: add riscv-iommu qtest/riscv-iommu-test: add init queues test hw/riscv/riscv-iommu: add DBG support hw/riscv/riscv-iommu: add ATS support hw/riscv/riscv-iommu: add Address Translation Cache (IOATC) test/qtest: add riscv-iommu-pci tests hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug hw/riscv: add riscv-iommu-pci reference device pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device hw/riscv: add RISC-V IOMMU base emulation hw/riscv: add riscv-iommu-bits.h exec/memtxattr: add process identifier to the transaction attributes target/riscv: Expose zicfiss extension as a cpu property disas/riscv: enable disassembly for compressed sspush/sspopchk disas/riscv: enable disassembly for zicfiss instructions target/riscv: compressed encodings for sspush and sspopchk target/riscv: implement zicfiss instructions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
92ec780519
65 changed files with 4790 additions and 139 deletions
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@ -52,6 +52,11 @@ typedef struct MemTxAttrs {
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unsigned int memory:1;
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/* Requester ID (for MSI for example) */
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unsigned int requester_id:16;
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/*
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* PID (PCI PASID) support: Limited to 8 bits process identifier.
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*/
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unsigned int pid:8;
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} MemTxAttrs;
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/* Bus masters which don't specify any attributes will get this,
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@ -24,6 +24,7 @@
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#include "qemu/fifo8.h"
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enum {
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SIFIVE_UART_TXFIFO = 0,
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@ -48,9 +49,13 @@ enum {
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SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */
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};
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#define SIFIVE_UART_TXFIFO_FULL 0x80000000
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#define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7)
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#define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7)
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#define SIFIVE_UART_RX_FIFO_SIZE 8
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#define SIFIVE_UART_TX_FIFO_SIZE 8
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#define TYPE_SIFIVE_UART "riscv.sifive.uart"
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OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART)
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@ -63,13 +68,20 @@ struct SiFiveUARTState {
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qemu_irq irq;
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MemoryRegion mmio;
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CharBackend chr;
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uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE];
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uint8_t rx_fifo_len;
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uint32_t txfifo;
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uint32_t ie;
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uint32_t ip;
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uint32_t txctrl;
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uint32_t rxctrl;
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uint32_t div;
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uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE];
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uint8_t rx_fifo_len;
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Fifo8 tx_fifo;
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QEMUTimer *fifo_trigger_handle;
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};
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SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
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@ -116,6 +116,7 @@ extern bool pci_available;
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#define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011
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#define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012
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#define PCI_DEVICE_ID_REDHAT_UFS 0x0013
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#define PCI_DEVICE_ID_REDHAT_RISCV_IOMMU 0x0014
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#define PCI_DEVICE_ID_REDHAT_QXL 0x0100
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#define FMT_PCIBUS PRIx64
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@ -56,7 +56,9 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
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hwaddr rom_base, hwaddr rom_size,
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uint64_t kernel_entry,
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uint64_t fdt_load_addr);
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void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
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void riscv_rom_copy_firmware_info(MachineState *machine,
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RISCVHartArrayState *harts,
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hwaddr rom_base,
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hwaddr rom_size,
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uint32_t reset_vec_size,
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uint64_t kernel_entry);
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@ -58,4 +58,33 @@ struct fw_dynamic_info {
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target_long boot_hart;
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};
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/** Representation dynamic info passed by previous booting stage */
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struct fw_dynamic_info32 {
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/** Info magic */
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int32_t magic;
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/** Info version */
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int32_t version;
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/** Next booting stage address */
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int32_t next_addr;
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/** Next booting stage mode */
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int32_t next_mode;
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/** Options for OpenSBI library */
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int32_t options;
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/**
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* Preferred boot HART id
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*
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* It is possible that the previous booting stage uses same link
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* address as the FW_DYNAMIC firmware. In this case, the relocation
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* lottery mechanism can potentially overwrite the previous booting
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* stage while other HARTs are still running in the previous booting
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* stage leading to boot-time crash. To avoid this boot-time crash,
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* the previous booting stage can specify last HART that will jump
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* to the FW_DYNAMIC firmware as the preferred boot HART.
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*
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* To avoid specifying a preferred boot HART, the previous booting
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* stage can set it to -1UL which will force the FW_DYNAMIC firmware
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* to use the relocation lottery mechanism.
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*/
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int32_t boot_hart;
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};
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#endif
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36
include/hw/riscv/iommu.h
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36
include/hw/riscv/iommu.h
Normal file
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@ -0,0 +1,36 @@
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/*
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* QEMU emulation of an RISC-V IOMMU
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*
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* Copyright (C) 2022-2023 Rivos Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_RISCV_IOMMU_H
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#define HW_RISCV_IOMMU_H
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#include "qemu/osdep.h"
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#include "qom/object.h"
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#define TYPE_RISCV_IOMMU "riscv-iommu"
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OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUState, RISCV_IOMMU)
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typedef struct RISCVIOMMUState RISCVIOMMUState;
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#define TYPE_RISCV_IOMMU_MEMORY_REGION "riscv-iommu-mr"
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typedef struct RISCVIOMMUSpace RISCVIOMMUSpace;
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#define TYPE_RISCV_IOMMU_PCI "riscv-iommu-pci"
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OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStatePci, RISCV_IOMMU_PCI)
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typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci;
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#endif
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