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tcg/s390x: Support MIE2 multiply single instructions

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The MIE2 facility adds 3-operand versions of multiply.

Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-02-24 01:28:44 +00:00
parent d84ca80462
commit 92c89a074c
3 changed files with 26 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

1
tcg/s390x/tcg-target-con-set.h
View file

@ -23,6 +23,7 @@ C_O1_I2(r, 0, ri)
C_O1_I2(r, 0, rI) C_O1_I2(r, 0, rI)
C_O1_I2(r, 0, rJ) C_O1_I2(r, 0, rJ)
C_O1_I2(r, r, ri) C_O1_I2(r, r, ri)
C_O1_I2(r, r, rJ)
C_O1_I2(r, rZ, r) C_O1_I2(r, rZ, r)
C_O1_I2(v, v, r) C_O1_I2(v, v, r)
C_O1_I2(v, v, v) C_O1_I2(v, v, v)

34
tcg/s390x/tcg-target.c.inc
View file

@ -175,6 +175,8 @@ typedef enum S390Opcode {
RRE_SLBGR = 0xb989, RRE_SLBGR = 0xb989,
RRE_XGR = 0xb982, RRE_XGR = 0xb982,
RRFa_MSRKC = 0xb9fd,
RRFa_MSGRKC = 0xb9ed,
RRFa_NRK = 0xb9f4, RRFa_NRK = 0xb9f4,
RRFa_NGRK = 0xb9e4, RRFa_NGRK = 0xb9e4,
RRFa_ORK = 0xb9f6, RRFa_ORK = 0xb9f6,
@ -2015,14 +2017,18 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break; break;
case INDEX_op_mul_i32: case INDEX_op_mul_i32:
a0 = args[0], a1 = args[1], a2 = (int32_t)args[2];
if (const_args[2]) { if (const_args[2]) {
if ((int32_t)args[2] == (int16_t)args[2]) { tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
tcg_out_insn(s, RI, MHI, args[0], args[2]); if (a2 == (int16_t)a2) {
tcg_out_insn(s, RI, MHI, a0, a2);
} else { } else {
tcg_out_insn(s, RIL, MSFI, args[0], args[2]); tcg_out_insn(s, RIL, MSFI, a0, a2);
} }
} else if (a0 == a1) {
tcg_out_insn(s, RRE, MSR, a0, a2);
} else { } else {
tcg_out_insn(s, RRE, MSR, args[0], args[2]); tcg_out_insn(s, RRFa, MSRKC, a0, a1, a2);
} }
break; break;
@ -2272,14 +2278,18 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break; break;
case INDEX_op_mul_i64: case INDEX_op_mul_i64:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) { if (const_args[2]) {
if (args[2] == (int16_t)args[2]) { tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
tcg_out_insn(s, RI, MGHI, args[0], args[2]); if (a2 == (int16_t)a2) {
tcg_out_insn(s, RI, MGHI, a0, a2);
} else { } else {
tcg_out_insn(s, RIL, MSGFI, args[0], args[2]); tcg_out_insn(s, RIL, MSGFI, a0, a2);
} }
} else if (a0 == a1) {
tcg_out_insn(s, RRE, MSGR, a0, a2);
} else { } else {
tcg_out_insn(s, RRE, MSGR, args[0], args[2]); tcg_out_insn(s, RRFa, MSGRKC, a0, a1, a2);
} }
break; break;
@ -2934,9 +2944,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
return C_O1_I2(r, r, ri); return C_O1_I2(r, r, ri);
case INDEX_op_mul_i32: case INDEX_op_mul_i32:
return C_O1_I2(r, 0, ri); return (HAVE_FACILITY(MISC_INSN_EXT2)
? C_O1_I2(r, r, ri)
: C_O1_I2(r, 0, ri));
case INDEX_op_mul_i64: case INDEX_op_mul_i64:
return C_O1_I2(r, 0, rJ); return (HAVE_FACILITY(MISC_INSN_EXT2)
? C_O1_I2(r, r, rJ)
: C_O1_I2(r, 0, rJ));
case INDEX_op_shl_i32: case INDEX_op_shl_i32:
case INDEX_op_shr_i32: case INDEX_op_shr_i32:

1
tcg/s390x/tcg-target.h
View file

@ -63,6 +63,7 @@ typedef enum TCGReg {
/* Facilities that are checked at runtime. */ /* Facilities that are checked at runtime. */
#define FACILITY_LOAD_ON_COND2 53 #define FACILITY_LOAD_ON_COND2 53
#define FACILITY_MISC_INSN_EXT2 58
#define FACILITY_VECTOR 129 #define FACILITY_VECTOR 129
#define FACILITY_VECTOR_ENH1 135 #define FACILITY_VECTOR_ENH1 135