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target/riscv: rvb: address calculation

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Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210505160620.15723-15-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Kito Cheng 2021-05-06 00:06:15 +08:00 • committed by Alistair Francis
parent c24f0422fb
commit 920a1f9955
3 changed files with 62 additions and 0 deletions
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24
target/riscv/insn_trans/trans_rvb.c.inc
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@ -226,6 +226,17 @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
return gen_shifti(ctx, a, gen_helper_gorc);
}
#define GEN_TRANS_SHADD(SHAMT) \
static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
{ \
REQUIRE_EXT(ctx, RVB); \
return gen_arith(ctx, a, gen_sh##SHAMT##add); \
}
GEN_TRANS_SHADD(1)
GEN_TRANS_SHADD(2)
GEN_TRANS_SHADD(3)
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@ -386,3 +397,16 @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
REQUIRE_EXT(ctx, RVB);
return gen_shiftiw(ctx, a, gen_gorcw);
}
#define GEN_TRANS_SHADD_UW(SHAMT) \
static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
arg_sh##SHAMT##add_uw *a) \
{ \
REQUIRE_64BIT(ctx); \
REQUIRE_EXT(ctx, RVB); \
return gen_arith(ctx, a, gen_sh##SHAMT##add_uw); \
}
GEN_TRANS_SHADD_UW(1)
GEN_TRANS_SHADD_UW(2)
GEN_TRANS_SHADD_UW(3)