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hw/riscv/riscv-iommu: add IOHPMCYCLES mmio write

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RISCV_IOMMU_REG_IOHPMCYCLES writes are done by
riscv_iommu_process_hpmcycle_write(), called by the mmio write callback
via riscv_iommu_process_hpm_writes().

Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250224190826.1858473-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Tomasz Jeznach 2025-02-24 16:08:22 -03:00 • committed by Alistair Francis
parent 2cf2a6c027
commit 91dd0bd021
3 changed files with 21 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

19
hw/riscv/riscv-iommu-hpm.c
View file

@ -262,3 +262,22 @@ void riscv_iommu_process_iocntinh_cy(RISCVIOMMUState *s, bool prev_cy_inh)
timer_del(s->hpm_timer);
}
}
void riscv_iommu_process_hpmcycle_write(RISCVIOMMUState *s)
{
const uint64_t val = riscv_iommu_reg_get64(s, RISCV_IOMMU_REG_IOHPMCYCLES);
const uint32_t ovf = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_IOCOUNTOVF);
/*
* Clear OF bit in IOCNTOVF if it's being cleared in IOHPMCYCLES register.
*/
if (get_field(ovf, RISCV_IOMMU_IOCOUNTOVF_CY) &&
!get_field(val, RISCV_IOMMU_IOHPMCYCLES_OVF)) {
riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_IOCOUNTOVF, 0,
RISCV_IOMMU_IOCOUNTOVF_CY);
}
s->hpmcycle_val = val & ~RISCV_IOMMU_IOHPMCYCLES_OVF;
s->hpmcycle_prev = get_cycles();
hpm_setup_timer(s, s->hpmcycle_val);
}

1
hw/riscv/riscv-iommu-hpm.h
View file

@ -27,5 +27,6 @@ void riscv_iommu_hpm_incr_ctr(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
unsigned event_id);
void riscv_iommu_hpm_timer_cb(void *priv);
void riscv_iommu_process_iocntinh_cy(RISCVIOMMUState *s, bool prev_cy_inh);
void riscv_iommu_process_hpmcycle_write(RISCVIOMMUState *s);
#endif

2
hw/riscv/riscv-iommu.c
View file

@ -2035,7 +2035,7 @@ static void riscv_iommu_process_hpm_writes(RISCVIOMMUState *s,
case RISCV_IOMMU_REG_IOHPMCYCLES:
case RISCV_IOMMU_REG_IOHPMCYCLES + 4:
/* not yet implemented */
riscv_iommu_process_hpmcycle_write(s);
break;
case RISCV_IOMMU_REG_IOHPMEVT_BASE ...