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target/riscv: rvb: shift ones

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Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-11-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Kito Cheng 2021-05-06 00:06:11 +08:00 • committed by Alistair Francis
parent 23cd17773b
commit 91d8fc6768
3 changed files with 74 additions and 0 deletions
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14
target/riscv/translate.c
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@ -613,6 +613,20 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
tcg_gen_andi_tl(ret, ret, 1);
}
static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
{
tcg_gen_not_tl(ret, arg1);
tcg_gen_shl_tl(ret, ret, arg2);
tcg_gen_not_tl(ret, ret);
}
static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
{
tcg_gen_not_tl(ret, arg1);
tcg_gen_shr_tl(ret, ret, arg2);
tcg_gen_not_tl(ret, ret);
}
static void gen_ctzw(TCGv ret, TCGv arg1)
{
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));