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target/arm: Convert CCMP, CCMN to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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729bca958d
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2 changed files with 25 additions and 47 deletions
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@ -761,8 +761,10 @@ RMIF 1 01 11010000 imm:6 00001 rn:5 0 mask:4
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SETF8 0 01 11010000 00000 000010 rn:5 01101
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SETF16 0 01 11010000 00000 010010 rn:5 01101
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# Conditional compare (regster)
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# Conditional compare (immediate)
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# Conditional compare
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CCMP sf:1 op:1 1 11010010 y:5 cond:4 imm:1 0 rn:5 0 nzcv:4
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# Conditional select
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# Data Processing (3-source)
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@ -8092,68 +8092,46 @@ static bool do_setf(DisasContext *s, int rn, int shift)
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TRANS_FEAT(SETF8, aa64_condm_4, do_setf, a->rn, 24)
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TRANS_FEAT(SETF16, aa64_condm_4, do_setf, a->rn, 16)
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/* Conditional compare (immediate / register)
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* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
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* +--+--+--+------------------------+--------+------+----+--+------+--+-----+
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* |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
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* +--+--+--+------------------------+--------+------+----+--+------+--+-----+
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* [1] y [0] [0]
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*/
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static void disas_cc(DisasContext *s, uint32_t insn)
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/* CCMP, CCMN */
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static bool trans_CCMP(DisasContext *s, arg_CCMP *a)
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{
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unsigned int sf, op, y, cond, rn, nzcv, is_imm;
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TCGv_i32 tcg_t0, tcg_t1, tcg_t2;
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TCGv_i64 tcg_tmp, tcg_y, tcg_rn;
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TCGv_i32 tcg_t0 = tcg_temp_new_i32();
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TCGv_i32 tcg_t1 = tcg_temp_new_i32();
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TCGv_i32 tcg_t2 = tcg_temp_new_i32();
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TCGv_i64 tcg_tmp = tcg_temp_new_i64();
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TCGv_i64 tcg_rn, tcg_y;
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DisasCompare c;
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if (!extract32(insn, 29, 1)) {
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unallocated_encoding(s);
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return;
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}
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if (insn & (1 << 10 | 1 << 4)) {
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unallocated_encoding(s);
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return;
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}
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sf = extract32(insn, 31, 1);
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op = extract32(insn, 30, 1);
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is_imm = extract32(insn, 11, 1);
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y = extract32(insn, 16, 5); /* y = rm (reg) or imm5 (imm) */
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cond = extract32(insn, 12, 4);
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rn = extract32(insn, 5, 5);
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nzcv = extract32(insn, 0, 4);
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unsigned nzcv;
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/* Set T0 = !COND. */
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tcg_t0 = tcg_temp_new_i32();
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arm_test_cc(&c, cond);
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arm_test_cc(&c, a->cond);
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tcg_gen_setcondi_i32(tcg_invert_cond(c.cond), tcg_t0, c.value, 0);
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/* Load the arguments for the new comparison. */
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if (is_imm) {
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tcg_y = tcg_temp_new_i64();
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tcg_gen_movi_i64(tcg_y, y);
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if (a->imm) {
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tcg_y = tcg_constant_i64(a->y);
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} else {
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tcg_y = cpu_reg(s, y);
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tcg_y = cpu_reg(s, a->y);
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}
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tcg_rn = cpu_reg(s, rn);
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tcg_rn = cpu_reg(s, a->rn);
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/* Set the flags for the new comparison. */
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tcg_tmp = tcg_temp_new_i64();
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if (op) {
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gen_sub_CC(sf, tcg_tmp, tcg_rn, tcg_y);
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if (a->op) {
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gen_sub_CC(a->sf, tcg_tmp, tcg_rn, tcg_y);
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} else {
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gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y);
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gen_add_CC(a->sf, tcg_tmp, tcg_rn, tcg_y);
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}
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/* If COND was false, force the flags to #nzcv. Compute two masks
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/*
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* If COND was false, force the flags to #nzcv. Compute two masks
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* to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
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* For tcg hosts that support ANDC, we can make do with just T1.
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* In either case, allow the tcg optimizer to delete any unused mask.
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*/
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tcg_t1 = tcg_temp_new_i32();
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tcg_t2 = tcg_temp_new_i32();
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tcg_gen_neg_i32(tcg_t1, tcg_t0);
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tcg_gen_subi_i32(tcg_t2, tcg_t0, 1);
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nzcv = a->nzcv;
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if (nzcv & 8) { /* N */
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tcg_gen_or_i32(cpu_NF, cpu_NF, tcg_t1);
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} else {
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@ -8190,6 +8168,7 @@ static void disas_cc(DisasContext *s, uint32_t insn)
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tcg_gen_and_i32(cpu_VF, cpu_VF, tcg_t2);
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}
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}
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return true;
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}
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/* Conditional select
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@ -8266,10 +8245,6 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
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}
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switch (op2) {
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case 0x2: /* Conditional compare */
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disas_cc(s, insn); /* both imm and reg forms */
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break;
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case 0x4: /* Conditional select */
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disas_cond_select(s, insn);
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break;
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@ -8277,6 +8252,7 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
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default:
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do_unallocated:
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case 0x0:
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case 0x2: /* Conditional compare */
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case 0x6: /* Data-processing */
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case 0x8 ... 0xf: /* (3 source) */
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unallocated_encoding(s);
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