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https://github.com/Motorhead1991/qemu.git
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tcg/i386: Use tcg_use_softmmu
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
e2b7a40d05
commit
915e1d52e2
1 changed files with 98 additions and 100 deletions
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@ -153,11 +153,8 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
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# define ALL_VECTOR_REGS 0x00ff0000u
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# define ALL_VECTOR_REGS 0x00ff0000u
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# define ALL_BYTEL_REGS 0x0000000fu
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# define ALL_BYTEL_REGS 0x0000000fu
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#endif
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#endif
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#ifdef CONFIG_SOFTMMU
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#define SOFTMMU_RESERVE_REGS \
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# define SOFTMMU_RESERVE_REGS ((1 << TCG_REG_L0) | (1 << TCG_REG_L1))
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(tcg_use_softmmu ? (1 << TCG_REG_L0) | (1 << TCG_REG_L1) : 0)
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#else
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# define SOFTMMU_RESERVE_REGS 0
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#endif
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/* For 64-bit, we always know that CMOV is available. */
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/* For 64-bit, we always know that CMOV is available. */
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#if TCG_TARGET_REG_BITS == 64
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#if TCG_TARGET_REG_BITS == 64
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@ -1933,7 +1930,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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return true;
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return true;
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}
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}
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#ifndef CONFIG_SOFTMMU
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#ifdef CONFIG_USER_ONLY
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static HostAddress x86_guest_base = {
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static HostAddress x86_guest_base = {
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.index = -1
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.index = -1
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};
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};
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@ -1949,6 +1946,7 @@ static inline int setup_guest_base_seg(void)
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}
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}
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return 0;
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return 0;
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}
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}
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#define setup_guest_base_seg setup_guest_base_seg
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#elif defined(__x86_64__) && \
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#elif defined(__x86_64__) && \
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(defined (__FreeBSD__) || defined (__FreeBSD_kernel__))
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(defined (__FreeBSD__) || defined (__FreeBSD_kernel__))
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# include <machine/sysarch.h>
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# include <machine/sysarch.h>
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@ -1959,13 +1957,14 @@ static inline int setup_guest_base_seg(void)
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}
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}
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return 0;
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return 0;
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}
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}
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#define setup_guest_base_seg setup_guest_base_seg
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#endif
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#else
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#else
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static inline int setup_guest_base_seg(void)
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# define x86_guest_base (*(HostAddress *)({ qemu_build_not_reached(); NULL; }))
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{
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#endif /* CONFIG_USER_ONLY */
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return 0;
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#ifndef setup_guest_base_seg
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}
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# define setup_guest_base_seg() 0
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#endif /* setup_guest_base_seg */
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#endif
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#endif /* !SOFTMMU */
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#define MIN_TLB_MASK_TABLE_OFS INT_MIN
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#define MIN_TLB_MASK_TABLE_OFS INT_MIN
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@ -1984,94 +1983,94 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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MemOp s_bits = opc & MO_SIZE;
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MemOp s_bits = opc & MO_SIZE;
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unsigned a_mask;
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unsigned a_mask;
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#ifdef CONFIG_SOFTMMU
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if (tcg_use_softmmu) {
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h->index = TCG_REG_L0;
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h->index = TCG_REG_L0;
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h->ofs = 0;
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h->ofs = 0;
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h->seg = 0;
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h->seg = 0;
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#else
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} else {
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*h = x86_guest_base;
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*h = x86_guest_base;
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#endif
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}
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h->base = addrlo;
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h->base = addrlo;
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h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128);
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h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128);
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a_mask = (1 << h->aa.align) - 1;
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a_mask = (1 << h->aa.align) - 1;
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#ifdef CONFIG_SOFTMMU
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if (tcg_use_softmmu) {
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int cmp_ofs = is_ld ? offsetof(CPUTLBEntry, addr_read)
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int cmp_ofs = is_ld ? offsetof(CPUTLBEntry, addr_read)
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: offsetof(CPUTLBEntry, addr_write);
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: offsetof(CPUTLBEntry, addr_write);
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TCGType ttype = TCG_TYPE_I32;
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TCGType ttype = TCG_TYPE_I32;
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TCGType tlbtype = TCG_TYPE_I32;
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TCGType tlbtype = TCG_TYPE_I32;
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int trexw = 0, hrexw = 0, tlbrexw = 0;
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int trexw = 0, hrexw = 0, tlbrexw = 0;
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unsigned mem_index = get_mmuidx(oi);
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unsigned mem_index = get_mmuidx(oi);
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unsigned s_mask = (1 << s_bits) - 1;
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unsigned s_mask = (1 << s_bits) - 1;
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int fast_ofs = tlb_mask_table_ofs(s, mem_index);
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int fast_ofs = tlb_mask_table_ofs(s, mem_index);
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int tlb_mask;
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int tlb_mask;
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ldst = new_ldst_label(s);
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->is_ld = is_ld;
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ldst->oi = oi;
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ldst->oi = oi;
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ldst->addrlo_reg = addrlo;
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ldst->addrlo_reg = addrlo;
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ldst->addrhi_reg = addrhi;
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ldst->addrhi_reg = addrhi;
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if (TCG_TARGET_REG_BITS == 64) {
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if (TCG_TARGET_REG_BITS == 64) {
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ttype = s->addr_type;
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ttype = s->addr_type;
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trexw = (ttype == TCG_TYPE_I32 ? 0 : P_REXW);
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trexw = (ttype == TCG_TYPE_I32 ? 0 : P_REXW);
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if (TCG_TYPE_PTR == TCG_TYPE_I64) {
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if (TCG_TYPE_PTR == TCG_TYPE_I64) {
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hrexw = P_REXW;
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hrexw = P_REXW;
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if (s->page_bits + s->tlb_dyn_max_bits > 32) {
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if (s->page_bits + s->tlb_dyn_max_bits > 32) {
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tlbtype = TCG_TYPE_I64;
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tlbtype = TCG_TYPE_I64;
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tlbrexw = P_REXW;
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tlbrexw = P_REXW;
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}
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}
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}
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}
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}
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}
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tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo);
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tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo);
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tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0,
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tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0,
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s->page_bits - CPU_TLB_ENTRY_BITS);
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s->page_bits - CPU_TLB_ENTRY_BITS);
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tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0,
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tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0,
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fast_ofs + offsetof(CPUTLBDescFast, mask));
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fast_ofs + offsetof(CPUTLBDescFast, mask));
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tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0,
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tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0,
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fast_ofs + offsetof(CPUTLBDescFast, table));
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fast_ofs + offsetof(CPUTLBDescFast, table));
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/*
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/*
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* If the required alignment is at least as large as the access, simply
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* If the required alignment is at least as large as the access,
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* copy the address and mask. For lesser alignments, check that we don't
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* simply copy the address and mask. For lesser alignments,
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* cross pages for the complete access.
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* check that we don't cross pages for the complete access.
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*/
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*/
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if (a_mask >= s_mask) {
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if (a_mask >= s_mask) {
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tcg_out_mov(s, ttype, TCG_REG_L1, addrlo);
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tcg_out_mov(s, ttype, TCG_REG_L1, addrlo);
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} else {
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} else {
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tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1,
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tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1,
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addrlo, s_mask - a_mask);
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addrlo, s_mask - a_mask);
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}
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}
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tlb_mask = s->page_mask | a_mask;
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tlb_mask = s->page_mask | a_mask;
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tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0);
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tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0);
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/* cmp 0(TCG_REG_L0), TCG_REG_L1 */
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/* cmp 0(TCG_REG_L0), TCG_REG_L1 */
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tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw,
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tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw,
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TCG_REG_L1, TCG_REG_L0, cmp_ofs);
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TCG_REG_L1, TCG_REG_L0, cmp_ofs);
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/* jne slow_path */
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tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
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ldst->label_ptr[0] = s->code_ptr;
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s->code_ptr += 4;
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if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I64) {
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/* cmp 4(TCG_REG_L0), addrhi */
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tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, TCG_REG_L0, cmp_ofs + 4);
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/* jne slow_path */
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/* jne slow_path */
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tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
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tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
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ldst->label_ptr[1] = s->code_ptr;
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ldst->label_ptr[0] = s->code_ptr;
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s->code_ptr += 4;
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s->code_ptr += 4;
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}
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/* TLB Hit. */
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if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I64) {
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0,
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/* cmp 4(TCG_REG_L0), addrhi */
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offsetof(CPUTLBEntry, addend));
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tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi,
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#else
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TCG_REG_L0, cmp_ofs + 4);
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if (a_mask) {
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/* jne slow_path */
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tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
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ldst->label_ptr[1] = s->code_ptr;
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s->code_ptr += 4;
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}
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/* TLB Hit. */
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0,
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offsetof(CPUTLBEntry, addend));
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} else if (a_mask) {
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ldst = new_ldst_label(s);
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ldst = new_ldst_label(s);
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ldst->is_ld = is_ld;
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ldst->is_ld = is_ld;
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@ -2085,7 +2084,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
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ldst->label_ptr[0] = s->code_ptr;
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ldst->label_ptr[0] = s->code_ptr;
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s->code_ptr += 4;
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s->code_ptr += 4;
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}
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}
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#endif
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return ldst;
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return ldst;
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}
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}
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@ -4140,35 +4138,35 @@ static void tcg_target_qemu_prologue(TCGContext *s)
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tcg_out_push(s, tcg_target_callee_save_regs[i]);
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tcg_out_push(s, tcg_target_callee_save_regs[i]);
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}
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}
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#if TCG_TARGET_REG_BITS == 32
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if (!tcg_use_softmmu && guest_base) {
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP,
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(ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4);
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tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
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/* jmp *tb. */
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tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP,
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(ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4
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+ stack_addend);
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#else
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# if !defined(CONFIG_SOFTMMU)
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if (guest_base) {
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int seg = setup_guest_base_seg();
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int seg = setup_guest_base_seg();
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if (seg != 0) {
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if (seg != 0) {
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x86_guest_base.seg = seg;
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x86_guest_base.seg = seg;
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} else if (guest_base == (int32_t)guest_base) {
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} else if (guest_base == (int32_t)guest_base) {
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x86_guest_base.ofs = guest_base;
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x86_guest_base.ofs = guest_base;
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} else {
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} else {
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assert(TCG_TARGET_REG_BITS == 64);
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/* Choose R12 because, as a base, it requires a SIB byte. */
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/* Choose R12 because, as a base, it requires a SIB byte. */
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x86_guest_base.index = TCG_REG_R12;
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x86_guest_base.index = TCG_REG_R12;
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tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base.index, guest_base);
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tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base.index, guest_base);
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tcg_regset_set_reg(s->reserved_regs, x86_guest_base.index);
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tcg_regset_set_reg(s->reserved_regs, x86_guest_base.index);
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}
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}
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}
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}
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# endif
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
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if (TCG_TARGET_REG_BITS == 32) {
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tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
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tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP,
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/* jmp *tb. */
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(ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4);
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tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]);
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tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
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#endif
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/* jmp *tb. */
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tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP,
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(ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4
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+ stack_addend);
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} else {
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tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
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tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
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/* jmp *tb. */
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tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]);
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}
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/*
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/*
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* Return path for goto_ptr. Set return value to 0, a-la exit_tb,
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* Return path for goto_ptr. Set return value to 0, a-la exit_tb,
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