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tcg/i386: Use tcg_use_softmmu

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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-01 08:13:44 -07:00
parent e2b7a40d05
commit 915e1d52e2
1 changed files with 98 additions and 100 deletions
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78
tcg/i386/tcg-target.c.inc
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@ -153,11 +153,8 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
# define ALL_VECTOR_REGS 0x00ff0000u # define ALL_VECTOR_REGS 0x00ff0000u
# define ALL_BYTEL_REGS 0x0000000fu # define ALL_BYTEL_REGS 0x0000000fu
#endif #endif
#ifdef CONFIG_SOFTMMU #define SOFTMMU_RESERVE_REGS \
# define SOFTMMU_RESERVE_REGS ((1 << TCG_REG_L0) | (1 << TCG_REG_L1)) (tcg_use_softmmu ? (1 << TCG_REG_L0) | (1 << TCG_REG_L1) : 0)
#else
# define SOFTMMU_RESERVE_REGS 0
#endif
/* For 64-bit, we always know that CMOV is available. */ /* For 64-bit, we always know that CMOV is available. */
#if TCG_TARGET_REG_BITS == 64 #if TCG_TARGET_REG_BITS == 64
@ -1933,7 +1930,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
return true; return true;
} }
#ifndef CONFIG_SOFTMMU #ifdef CONFIG_USER_ONLY
static HostAddress x86_guest_base = { static HostAddress x86_guest_base = {
.index = -1 .index = -1
}; };
@ -1949,6 +1946,7 @@ static inline int setup_guest_base_seg(void)
} }
return 0; return 0;
} }
#define setup_guest_base_seg setup_guest_base_seg
#elif defined(__x86_64__) && \ #elif defined(__x86_64__) && \
(defined (__FreeBSD__) || defined (__FreeBSD_kernel__)) (defined (__FreeBSD__) || defined (__FreeBSD_kernel__))
# include <machine/sysarch.h> # include <machine/sysarch.h>
@ -1959,13 +1957,14 @@ static inline int setup_guest_base_seg(void)
} }
return 0; return 0;
} }
#define setup_guest_base_seg setup_guest_base_seg
#endif
#else #else
static inline int setup_guest_base_seg(void) # define x86_guest_base (*(HostAddress *)({ qemu_build_not_reached(); NULL; }))
{ #endif /* CONFIG_USER_ONLY */
return 0; #ifndef setup_guest_base_seg
} # define setup_guest_base_seg() 0
#endif /* setup_guest_base_seg */ #endif
#endif /* !SOFTMMU */
#define MIN_TLB_MASK_TABLE_OFS INT_MIN #define MIN_TLB_MASK_TABLE_OFS INT_MIN
@ -1984,18 +1983,18 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
MemOp s_bits = opc & MO_SIZE; MemOp s_bits = opc & MO_SIZE;
unsigned a_mask; unsigned a_mask;
#ifdef CONFIG_SOFTMMU if (tcg_use_softmmu) {
h->index = TCG_REG_L0; h->index = TCG_REG_L0;
h->ofs = 0; h->ofs = 0;
h->seg = 0; h->seg = 0;
#else } else {
*h = x86_guest_base; *h = x86_guest_base;
#endif }
h->base = addrlo; h->base = addrlo;
h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128); h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits == MO_128);
a_mask = (1 << h->aa.align) - 1; a_mask = (1 << h->aa.align) - 1;
#ifdef CONFIG_SOFTMMU if (tcg_use_softmmu) {
int cmp_ofs = is_ld ? offsetof(CPUTLBEntry, addr_read) int cmp_ofs = is_ld ? offsetof(CPUTLBEntry, addr_read)
: offsetof(CPUTLBEntry, addr_write); : offsetof(CPUTLBEntry, addr_write);
TCGType ttype = TCG_TYPE_I32; TCGType ttype = TCG_TYPE_I32;
@ -2035,9 +2034,9 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
fast_ofs + offsetof(CPUTLBDescFast, table)); fast_ofs + offsetof(CPUTLBDescFast, table));
/* /*
* If the required alignment is at least as large as the access, simply * If the required alignment is at least as large as the access,
* copy the address and mask. For lesser alignments, check that we don't * simply copy the address and mask. For lesser alignments,
* cross pages for the complete access. * check that we don't cross pages for the complete access.
*/ */
if (a_mask >= s_mask) { if (a_mask >= s_mask) {
tcg_out_mov(s, ttype, TCG_REG_L1, addrlo); tcg_out_mov(s, ttype, TCG_REG_L1, addrlo);
@ -2059,7 +2058,8 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I64) { if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I64) {
/* cmp 4(TCG_REG_L0), addrhi */ /* cmp 4(TCG_REG_L0), addrhi */
tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, TCG_REG_L0, cmp_ofs + 4); tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi,
TCG_REG_L0, cmp_ofs + 4);
/* jne slow_path */ /* jne slow_path */
tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
@ -2070,8 +2070,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
/* TLB Hit. */ /* TLB Hit. */
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0, tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0,
offsetof(CPUTLBEntry, addend)); offsetof(CPUTLBEntry, addend));
#else } else if (a_mask) {
if (a_mask) {
ldst = new_ldst_label(s); ldst = new_ldst_label(s);
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
@ -2085,7 +2084,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst->label_ptr[0] = s->code_ptr; ldst->label_ptr[0] = s->code_ptr;
s->code_ptr += 4; s->code_ptr += 4;
} }
#endif
return ldst; return ldst;
} }
@ -4140,7 +4138,22 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tcg_out_push(s, tcg_target_callee_save_regs[i]); tcg_out_push(s, tcg_target_callee_save_regs[i]);
} }
#if TCG_TARGET_REG_BITS == 32 if (!tcg_use_softmmu && guest_base) {
int seg = setup_guest_base_seg();
if (seg != 0) {
x86_guest_base.seg = seg;
} else if (guest_base == (int32_t)guest_base) {
x86_guest_base.ofs = guest_base;
} else {
assert(TCG_TARGET_REG_BITS == 64);
/* Choose R12 because, as a base, it requires a SIB byte. */
x86_guest_base.index = TCG_REG_R12;
tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base.index, guest_base);
tcg_regset_set_reg(s->reserved_regs, x86_guest_base.index);
}
}
if (TCG_TARGET_REG_BITS == 32) {
tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP,
(ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4); (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4);
tcg_out_addi(s, TCG_REG_ESP, -stack_addend); tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
@ -4148,27 +4161,12 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP, tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP,
(ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4 (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4
+ stack_addend); + stack_addend);
#else
# if !defined(CONFIG_SOFTMMU)
if (guest_base) {
int seg = setup_guest_base_seg();
if (seg != 0) {
x86_guest_base.seg = seg;
} else if (guest_base == (int32_t)guest_base) {
x86_guest_base.ofs = guest_base;
} else { } else {
/* Choose R12 because, as a base, it requires a SIB byte. */
x86_guest_base.index = TCG_REG_R12;
tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base.index, guest_base);
tcg_regset_set_reg(s->reserved_regs, x86_guest_base.index);
}
}
# endif
tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
tcg_out_addi(s, TCG_REG_ESP, -stack_addend); tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
/* jmp *tb. */ /* jmp *tb. */
tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]); tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]);
#endif }
/* /*
* Return path for goto_ptr. Set return value to 0, a-la exit_tb, * Return path for goto_ptr. Set return value to 0, a-la exit_tb,