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target/sparc: Fix FMUL8x16

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This instruction has f32 as source1, which alters the
decoding of the register number, which means we've been
passing the wrong data for odd register numbers.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240502165528.244004-4-richard.henderson@linaro.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
This commit is contained in:
Richard Henderson 2024-05-02 09:55:24 -07:00 • committed by Mark Cave-Ayland
parent 7b616f36de
commit 9157dccc7e
3 changed files with 26 additions and 6 deletions
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9
target/sparc/vis_helper.c
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@ -94,16 +94,17 @@ uint64_t helper_fpmerge(uint64_t src1, uint64_t src2)
return d.ll;
}
uint64_t helper_fmul8x16(uint64_t src1, uint64_t src2)
uint64_t helper_fmul8x16(uint32_t src1, uint64_t src2)
{
VIS64 s, d;
VIS64 d;
VIS32 s;
uint32_t tmp;
s.ll = src1;
s.l = src1;
d.ll = src2;
#define PMUL(r) \
tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B32(r); \
if ((tmp & 0xff) > 0x7f) { \
tmp += 0x100; \
} \