mirror of
https://github.com/Motorhead1991/qemu.git
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Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl
parent
636aa20056
commit
90e189ece1
12 changed files with 269 additions and 245 deletions
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@ -267,7 +267,7 @@ static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
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uint32_t ret;
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#ifdef DEBUG_OPBA
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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opba = opaque;
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switch (addr) {
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@ -291,7 +291,8 @@ static void opba_writeb (void *opaque,
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ppc4xx_opba_t *opba;
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#ifdef DEBUG_OPBA
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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opba = opaque;
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switch (addr) {
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@ -311,7 +312,7 @@ static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
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uint32_t ret;
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#ifdef DEBUG_OPBA
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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ret = opba_readb(opaque, addr) << 8;
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ret |= opba_readb(opaque, addr + 1);
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@ -323,7 +324,8 @@ static void opba_writew (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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#ifdef DEBUG_OPBA
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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opba_writeb(opaque, addr, value >> 8);
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opba_writeb(opaque, addr + 1, value);
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@ -334,7 +336,7 @@ static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
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uint32_t ret;
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#ifdef DEBUG_OPBA
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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ret = opba_readb(opaque, addr) << 24;
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ret |= opba_readb(opaque, addr + 1) << 16;
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@ -346,7 +348,8 @@ static void opba_writel (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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#ifdef DEBUG_OPBA
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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opba_writeb(opaque, addr, value >> 24);
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opba_writeb(opaque, addr + 1, value >> 16);
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@ -380,7 +383,7 @@ static void ppc4xx_opba_init(target_phys_addr_t base)
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opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
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#ifdef DEBUG_OPBA
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printf("%s: offset " PADDRX "\n", __func__, base);
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printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
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#endif
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io = cpu_register_io_memory(opba_read, opba_write, opba);
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cpu_register_physical_memory(base, 0x002, io);
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@ -744,7 +747,7 @@ static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
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gpio = opaque;
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#ifdef DEBUG_GPIO
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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return 0;
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@ -757,7 +760,8 @@ static void ppc405_gpio_writeb (void *opaque,
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gpio = opaque;
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#ifdef DEBUG_GPIO
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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}
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@ -767,7 +771,7 @@ static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
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gpio = opaque;
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#ifdef DEBUG_GPIO
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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return 0;
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@ -780,7 +784,8 @@ static void ppc405_gpio_writew (void *opaque,
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gpio = opaque;
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#ifdef DEBUG_GPIO
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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}
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@ -790,7 +795,7 @@ static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
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gpio = opaque;
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#ifdef DEBUG_GPIO
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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return 0;
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@ -803,7 +808,8 @@ static void ppc405_gpio_writel (void *opaque,
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gpio = opaque;
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#ifdef DEBUG_GPIO
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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}
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@ -833,7 +839,7 @@ static void ppc405_gpio_init(target_phys_addr_t base)
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gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
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#ifdef DEBUG_GPIO
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printf("%s: offset " PADDRX "\n", __func__, base);
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printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
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#endif
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io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio);
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cpu_register_physical_memory(base, 0x038, io);
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@ -1035,7 +1041,7 @@ static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
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uint32_t ret;
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#ifdef DEBUG_I2C
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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i2c = opaque;
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switch (addr) {
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@ -1090,7 +1096,7 @@ static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
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break;
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}
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#ifdef DEBUG_I2C
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printf("%s: addr " PADDRX " %02" PRIx32 "\n", __func__, addr, ret);
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printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
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#endif
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return ret;
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@ -1102,7 +1108,8 @@ static void ppc4xx_i2c_writeb (void *opaque,
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ppc4xx_i2c_t *i2c;
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#ifdef DEBUG_I2C
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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i2c = opaque;
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switch (addr) {
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@ -1160,7 +1167,7 @@ static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
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uint32_t ret;
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#ifdef DEBUG_I2C
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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ret = ppc4xx_i2c_readb(opaque, addr) << 8;
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ret |= ppc4xx_i2c_readb(opaque, addr + 1);
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@ -1172,7 +1179,8 @@ static void ppc4xx_i2c_writew (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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#ifdef DEBUG_I2C
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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ppc4xx_i2c_writeb(opaque, addr, value >> 8);
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ppc4xx_i2c_writeb(opaque, addr + 1, value);
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@ -1183,7 +1191,7 @@ static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
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uint32_t ret;
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#ifdef DEBUG_I2C
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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ret = ppc4xx_i2c_readb(opaque, addr) << 24;
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ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
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@ -1197,7 +1205,8 @@ static void ppc4xx_i2c_writel (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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#ifdef DEBUG_I2C
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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ppc4xx_i2c_writeb(opaque, addr, value >> 24);
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ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
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@ -1241,7 +1250,7 @@ static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
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i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
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i2c->irq = irq;
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#ifdef DEBUG_I2C
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printf("%s: offset " PADDRX "\n", __func__, base);
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printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
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#endif
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io = cpu_register_io_memory(i2c_read, i2c_write, i2c);
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cpu_register_physical_memory(base, 0x011, io);
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@ -1269,7 +1278,7 @@ struct ppc4xx_gpt_t {
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static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
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{
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#ifdef DEBUG_GPT
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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/* XXX: generate a bus fault */
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return -1;
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@ -1279,7 +1288,8 @@ static void ppc4xx_gpt_writeb (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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#ifdef DEBUG_I2C
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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/* XXX: generate a bus fault */
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}
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@ -1287,7 +1297,7 @@ static void ppc4xx_gpt_writeb (void *opaque,
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static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
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{
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#ifdef DEBUG_GPT
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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/* XXX: generate a bus fault */
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return -1;
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@ -1297,7 +1307,8 @@ static void ppc4xx_gpt_writew (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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#ifdef DEBUG_I2C
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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/* XXX: generate a bus fault */
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}
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@ -1361,7 +1372,7 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
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int idx;
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#ifdef DEBUG_GPT
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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gpt = opaque;
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switch (addr) {
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@ -1416,7 +1427,8 @@ static void ppc4xx_gpt_writel (void *opaque,
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int idx;
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#ifdef DEBUG_I2C
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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gpt = opaque;
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switch (addr) {
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@ -1522,7 +1534,7 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
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}
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gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
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#ifdef DEBUG_GPT
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printf("%s: offset " PADDRX "\n", __func__, base);
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printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
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#endif
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io = cpu_register_io_memory(gpt_read, gpt_write, gpt);
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cpu_register_physical_memory(base, 0x0d4, io);
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