mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-07 17:53:56 -06:00
Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl
parent
636aa20056
commit
90e189ece1
12 changed files with 269 additions and 245 deletions
28
hw/ppc.c
28
hw/ppc.c
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@ -795,9 +795,9 @@ static void cpu_4xx_fit_cb (void *opaque)
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env->spr[SPR_40x_TSR] |= 1 << 26;
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if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
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ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
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LOG_TB("%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
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(int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
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env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
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LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
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(int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
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env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
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}
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/* Programmable interval timer */
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@ -841,12 +841,12 @@ static void cpu_4xx_pit_cb (void *opaque)
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if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
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ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
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start_stop_pit(env, tb_env, 1);
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LOG_TB("%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
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"%016" PRIx64 "\n", __func__,
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(int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
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(int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
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env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
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ppcemb_timer->pit_reload);
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LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " "
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"%016" PRIx64 "\n", __func__,
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(int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
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(int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
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env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
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ppcemb_timer->pit_reload);
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}
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/* Watchdog timer */
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@ -881,8 +881,8 @@ static void cpu_4xx_wdt_cb (void *opaque)
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next = now + muldiv64(next, ticks_per_sec, tb_env->decr_freq);
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if (next == now)
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next++;
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LOG_TB("%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
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env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
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LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
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env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
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switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
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case 0x0:
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case 0x1:
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@ -924,7 +924,7 @@ void store_40x_pit (CPUState *env, target_ulong val)
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tb_env = env->tb_env;
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ppcemb_timer = tb_env->opaque;
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LOG_TB("%s val" ADDRX "\n", __func__, val);
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LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val);
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ppcemb_timer->pit_reload = val;
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start_stop_pit(env, tb_env, 0);
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}
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@ -936,7 +936,7 @@ target_ulong load_40x_pit (CPUState *env)
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void store_booke_tsr (CPUState *env, target_ulong val)
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{
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LOG_TB("%s: val " ADDRX "\n", __func__, val);
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LOG_TB("%s: val " TARGET_FMT_lx "\n", __func__, val);
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env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
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if (val & 0x80000000)
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ppc_set_irq(env, PPC_INTERRUPT_PIT, 0);
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@ -947,7 +947,7 @@ void store_booke_tcr (CPUState *env, target_ulong val)
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ppc_tb_t *tb_env;
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tb_env = env->tb_env;
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LOG_TB("%s: val " ADDRX "\n", __func__, val);
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LOG_TB("%s: val " TARGET_FMT_lx "\n", __func__, val);
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env->spr[SPR_40x_TCR] = val & 0xFFC00000;
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start_stop_pit(env, tb_env, 1);
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cpu_4xx_wdt_cb(env);
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@ -221,8 +221,8 @@ static void ref405ep_init (ram_addr_t ram_size,
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bios_offset = qemu_ram_alloc(bios_size);
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fl_sectors = (bios_size + 65535) >> 16;
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#ifdef DEBUG_BOARD_INIT
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printf("Register parallel flash %d size " ADDRX " at offset %08lx "
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" addr " ADDRX " '%s' %d\n",
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printf("Register parallel flash %d size " TARGET_FMT_lx
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" at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
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fl_idx, bios_size, bios_offset, -bios_size,
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bdrv_get_device_name(dinfo->bdrv), fl_sectors);
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#endif
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@ -536,8 +536,8 @@ static void taihu_405ep_init(ram_addr_t ram_size,
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fl_sectors = (bios_size + 65535) >> 16;
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bios_offset = qemu_ram_alloc(bios_size);
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#ifdef DEBUG_BOARD_INIT
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printf("Register parallel flash %d size " ADDRX " at offset %08lx "
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" addr " ADDRX " '%s' %d\n",
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printf("Register parallel flash %d size " TARGET_FMT_lx
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" at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
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fl_idx, bios_size, bios_offset, -bios_size,
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bdrv_get_device_name(dinfo->bdrv), fl_sectors);
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#endif
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@ -577,8 +577,8 @@ static void taihu_405ep_init(ram_addr_t ram_size,
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bios_size = 32 * 1024 * 1024;
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fl_sectors = (bios_size + 65535) >> 16;
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#ifdef DEBUG_BOARD_INIT
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printf("Register parallel flash %d size " ADDRX " at offset %08lx "
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" addr " ADDRX " '%s'\n",
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printf("Register parallel flash %d size " TARGET_FMT_lx
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" at offset %08lx addr " TARGET_FMT_lx " '%s'\n",
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fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
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bdrv_get_device_name(dinfo->bdrv));
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#endif
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@ -267,7 +267,7 @@ static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
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uint32_t ret;
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#ifdef DEBUG_OPBA
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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opba = opaque;
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switch (addr) {
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@ -291,7 +291,8 @@ static void opba_writeb (void *opaque,
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ppc4xx_opba_t *opba;
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#ifdef DEBUG_OPBA
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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opba = opaque;
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switch (addr) {
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@ -311,7 +312,7 @@ static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
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uint32_t ret;
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#ifdef DEBUG_OPBA
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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ret = opba_readb(opaque, addr) << 8;
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ret |= opba_readb(opaque, addr + 1);
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@ -323,7 +324,8 @@ static void opba_writew (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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#ifdef DEBUG_OPBA
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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opba_writeb(opaque, addr, value >> 8);
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opba_writeb(opaque, addr + 1, value);
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@ -334,7 +336,7 @@ static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
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uint32_t ret;
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#ifdef DEBUG_OPBA
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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ret = opba_readb(opaque, addr) << 24;
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ret |= opba_readb(opaque, addr + 1) << 16;
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@ -346,7 +348,8 @@ static void opba_writel (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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#ifdef DEBUG_OPBA
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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opba_writeb(opaque, addr, value >> 24);
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opba_writeb(opaque, addr + 1, value >> 16);
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@ -380,7 +383,7 @@ static void ppc4xx_opba_init(target_phys_addr_t base)
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opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
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#ifdef DEBUG_OPBA
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printf("%s: offset " PADDRX "\n", __func__, base);
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printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
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#endif
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io = cpu_register_io_memory(opba_read, opba_write, opba);
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cpu_register_physical_memory(base, 0x002, io);
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@ -744,7 +747,7 @@ static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
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gpio = opaque;
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#ifdef DEBUG_GPIO
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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return 0;
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@ -757,7 +760,8 @@ static void ppc405_gpio_writeb (void *opaque,
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gpio = opaque;
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#ifdef DEBUG_GPIO
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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}
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@ -767,7 +771,7 @@ static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
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gpio = opaque;
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#ifdef DEBUG_GPIO
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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return 0;
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@ -780,7 +784,8 @@ static void ppc405_gpio_writew (void *opaque,
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gpio = opaque;
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#ifdef DEBUG_GPIO
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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}
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@ -790,7 +795,7 @@ static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
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gpio = opaque;
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#ifdef DEBUG_GPIO
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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return 0;
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@ -803,7 +808,8 @@ static void ppc405_gpio_writel (void *opaque,
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gpio = opaque;
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#ifdef DEBUG_GPIO
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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}
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@ -833,7 +839,7 @@ static void ppc405_gpio_init(target_phys_addr_t base)
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gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
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#ifdef DEBUG_GPIO
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printf("%s: offset " PADDRX "\n", __func__, base);
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printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
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#endif
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io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio);
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cpu_register_physical_memory(base, 0x038, io);
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@ -1035,7 +1041,7 @@ static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
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uint32_t ret;
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#ifdef DEBUG_I2C
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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i2c = opaque;
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switch (addr) {
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@ -1090,7 +1096,7 @@ static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
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break;
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}
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#ifdef DEBUG_I2C
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printf("%s: addr " PADDRX " %02" PRIx32 "\n", __func__, addr, ret);
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printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
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#endif
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return ret;
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@ -1102,7 +1108,8 @@ static void ppc4xx_i2c_writeb (void *opaque,
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ppc4xx_i2c_t *i2c;
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#ifdef DEBUG_I2C
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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i2c = opaque;
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switch (addr) {
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@ -1160,7 +1167,7 @@ static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
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uint32_t ret;
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#ifdef DEBUG_I2C
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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ret = ppc4xx_i2c_readb(opaque, addr) << 8;
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ret |= ppc4xx_i2c_readb(opaque, addr + 1);
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@ -1172,7 +1179,8 @@ static void ppc4xx_i2c_writew (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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#ifdef DEBUG_I2C
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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ppc4xx_i2c_writeb(opaque, addr, value >> 8);
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ppc4xx_i2c_writeb(opaque, addr + 1, value);
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@ -1183,7 +1191,7 @@ static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
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uint32_t ret;
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#ifdef DEBUG_I2C
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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ret = ppc4xx_i2c_readb(opaque, addr) << 24;
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ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
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@ -1197,7 +1205,8 @@ static void ppc4xx_i2c_writel (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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#ifdef DEBUG_I2C
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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ppc4xx_i2c_writeb(opaque, addr, value >> 24);
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ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
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@ -1241,7 +1250,7 @@ static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
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i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
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i2c->irq = irq;
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#ifdef DEBUG_I2C
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printf("%s: offset " PADDRX "\n", __func__, base);
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printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
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#endif
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io = cpu_register_io_memory(i2c_read, i2c_write, i2c);
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cpu_register_physical_memory(base, 0x011, io);
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@ -1269,7 +1278,7 @@ struct ppc4xx_gpt_t {
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static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
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{
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#ifdef DEBUG_GPT
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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/* XXX: generate a bus fault */
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return -1;
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@ -1279,7 +1288,8 @@ static void ppc4xx_gpt_writeb (void *opaque,
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target_phys_addr_t addr, uint32_t value)
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{
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#ifdef DEBUG_I2C
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printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
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printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
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value);
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#endif
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/* XXX: generate a bus fault */
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}
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@ -1287,7 +1297,7 @@ static void ppc4xx_gpt_writeb (void *opaque,
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static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
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{
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#ifdef DEBUG_GPT
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printf("%s: addr " PADDRX "\n", __func__, addr);
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printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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#endif
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/* XXX: generate a bus fault */
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return -1;
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@ -1297,7 +1307,8 @@ static void ppc4xx_gpt_writew (void *opaque,
|
|||
target_phys_addr_t addr, uint32_t value)
|
||||
{
|
||||
#ifdef DEBUG_I2C
|
||||
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
|
||||
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
|
||||
value);
|
||||
#endif
|
||||
/* XXX: generate a bus fault */
|
||||
}
|
||||
|
|
@ -1361,7 +1372,7 @@ static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
|
|||
int idx;
|
||||
|
||||
#ifdef DEBUG_GPT
|
||||
printf("%s: addr " PADDRX "\n", __func__, addr);
|
||||
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
||||
#endif
|
||||
gpt = opaque;
|
||||
switch (addr) {
|
||||
|
|
@ -1416,7 +1427,8 @@ static void ppc4xx_gpt_writel (void *opaque,
|
|||
int idx;
|
||||
|
||||
#ifdef DEBUG_I2C
|
||||
printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
|
||||
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
|
||||
value);
|
||||
#endif
|
||||
gpt = opaque;
|
||||
switch (addr) {
|
||||
|
|
@ -1522,7 +1534,7 @@ static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
|
|||
}
|
||||
gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
|
||||
#ifdef DEBUG_GPT
|
||||
printf("%s: offset " PADDRX "\n", __func__, base);
|
||||
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
|
||||
#endif
|
||||
io = cpu_register_io_memory(gpt_read, gpt_write, gpt);
|
||||
cpu_register_physical_memory(base, 0x0d4, io);
|
||||
|
|
|
|||
|
|
@ -235,7 +235,7 @@ static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
|
|||
|
||||
uic = opaque;
|
||||
dcrn -= uic->dcr_base;
|
||||
LOG_UIC("%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
|
||||
LOG_UIC("%s: dcr %d val " TARGET_FMT_lx "\n", __func__, dcrn, val);
|
||||
switch (dcrn) {
|
||||
case DCR_UICSR:
|
||||
uic->uicsr &= ~val;
|
||||
|
|
@ -368,7 +368,8 @@ static uint32_t sdram_bcr (target_phys_addr_t ram_base,
|
|||
bcr = 0x000C0000;
|
||||
break;
|
||||
default:
|
||||
printf("%s: invalid RAM size " PADDRX "\n", __func__, ram_size);
|
||||
printf("%s: invalid RAM size " TARGET_FMT_plx "\n", __func__,
|
||||
ram_size);
|
||||
return 0x00000000;
|
||||
}
|
||||
bcr |= ram_base & 0xFF800000;
|
||||
|
|
@ -401,7 +402,7 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
|
|||
if (*bcrp & 0x00000001) {
|
||||
/* Unmap RAM */
|
||||
#ifdef DEBUG_SDRAM
|
||||
printf("%s: unmap RAM area " PADDRX " " ADDRX "\n",
|
||||
printf("%s: unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
|
||||
__func__, sdram_base(*bcrp), sdram_size(*bcrp));
|
||||
#endif
|
||||
cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
|
||||
|
|
@ -410,7 +411,7 @@ static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
|
|||
*bcrp = bcr & 0xFFDEE001;
|
||||
if (enabled && (bcr & 0x00000001)) {
|
||||
#ifdef DEBUG_SDRAM
|
||||
printf("%s: Map RAM area " PADDRX " " ADDRX "\n",
|
||||
printf("%s: Map RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
|
||||
__func__, sdram_base(bcr), sdram_size(bcr));
|
||||
#endif
|
||||
cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
|
||||
|
|
@ -439,7 +440,7 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
|
|||
|
||||
for (i = 0; i < sdram->nbanks; i++) {
|
||||
#ifdef DEBUG_SDRAM
|
||||
printf("%s: Unmap RAM area " PADDRX " " ADDRX "\n",
|
||||
printf("%s: Unmap RAM area " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
|
||||
__func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
|
||||
#endif
|
||||
cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
|
||||
|
|
|
|||
|
|
@ -112,7 +112,10 @@ static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
|
|||
static void _PPC_intack_write (void *opaque,
|
||||
target_phys_addr_t addr, uint32_t value)
|
||||
{
|
||||
// printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
|
||||
#if 0
|
||||
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
|
||||
value);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
|
||||
|
|
@ -121,7 +124,10 @@ static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
|
|||
|
||||
if ((addr & 0xf) == 0)
|
||||
retval = pic_intack_read(isa_pic);
|
||||
// printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
|
||||
#if 0
|
||||
printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
|
||||
retval);
|
||||
#endif
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
|
@ -191,7 +197,8 @@ static struct {
|
|||
static void PPC_XCSR_writeb (void *opaque,
|
||||
target_phys_addr_t addr, uint32_t value)
|
||||
{
|
||||
printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
|
||||
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
|
||||
value);
|
||||
}
|
||||
|
||||
static void PPC_XCSR_writew (void *opaque,
|
||||
|
|
@ -200,7 +207,8 @@ static void PPC_XCSR_writew (void *opaque,
|
|||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
value = bswap16(value);
|
||||
#endif
|
||||
printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
|
||||
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
|
||||
value);
|
||||
}
|
||||
|
||||
static void PPC_XCSR_writel (void *opaque,
|
||||
|
|
@ -209,14 +217,16 @@ static void PPC_XCSR_writel (void *opaque,
|
|||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
value = bswap32(value);
|
||||
#endif
|
||||
printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
|
||||
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
|
||||
value);
|
||||
}
|
||||
|
||||
static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
uint32_t retval = 0;
|
||||
|
||||
printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
|
||||
printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
|
||||
retval);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
|
@ -225,7 +235,8 @@ static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
|
|||
{
|
||||
uint32_t retval = 0;
|
||||
|
||||
printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
|
||||
printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
|
||||
retval);
|
||||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
retval = bswap16(retval);
|
||||
#endif
|
||||
|
|
@ -237,7 +248,8 @@ static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
|
|||
{
|
||||
uint32_t retval = 0;
|
||||
|
||||
printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
|
||||
printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
|
||||
retval);
|
||||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
retval = bswap32(retval);
|
||||
#endif
|
||||
|
|
@ -469,7 +481,7 @@ static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
|
|||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
value = bswap16(value);
|
||||
#endif
|
||||
PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
|
||||
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
|
||||
cpu_outw(NULL, addr, value);
|
||||
}
|
||||
|
||||
|
|
@ -483,7 +495,7 @@ static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
|
|||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
ret = bswap16(ret);
|
||||
#endif
|
||||
PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
|
||||
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -497,7 +509,7 @@ static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
|
|||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
value = bswap32(value);
|
||||
#endif
|
||||
PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
|
||||
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
|
||||
cpu_outl(NULL, addr, value);
|
||||
}
|
||||
|
||||
|
|
@ -511,7 +523,7 @@ static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
|
|||
#ifdef TARGET_WORDS_BIGENDIAN
|
||||
ret = bswap32(ret);
|
||||
#endif
|
||||
PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
|
||||
PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue