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hw/pci-host: Constify all Property

Browse source 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-13 16:35:23 +00:00
parent 196fd15f31
commit 909a5c0afa
17 changed files with 19 additions and 19 deletions
Download patch file Download diff file Expand all files Collapse all files

2
hw/pci-host/dino.c
View file

@ -492,7 +492,7 @@ static void dino_pcihost_init(Object *obj)
qdev_init_gpio_in(DEVICE(obj), dino_set_irq, DINO_IRQS);
}
static Property dino_pcihost_properties[] = {
static const Property dino_pcihost_properties[] = {
DEFINE_PROP_LINK("memory-as", DinoState, memory_as, TYPE_MEMORY_REGION,
MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),

2
hw/pci-host/gpex.c
View file

@ -147,7 +147,7 @@ static const char *gpex_host_root_bus_path(PCIHostState *host_bridge,
return "0000:00";
}
static Property gpex_host_properties[] = {
static const Property gpex_host_properties[] = {
/*
* Permit CPU accesses to unmapped areas of the PIO and MMIO windows
* (discarding writes and returning -1 for reads) rather than aborting.

2
hw/pci-host/grackle.c
View file

@ -129,7 +129,7 @@ static char *grackle_ofw_unit_address(const SysBusDevice *dev)
return g_strdup_printf("%x", s->ofw_addr);
}
static Property grackle_properties[] = {
static const Property grackle_properties[] = {
DEFINE_PROP_UINT32("ofw-addr", GrackleState, ofw_addr, -1),
DEFINE_PROP_END_OF_LIST()
};

2
hw/pci-host/gt64120.c
View file

@ -1274,7 +1274,7 @@ static const TypeInfo gt64120_pci_info = {
},
};
static Property gt64120_properties[] = {
static const Property gt64120_properties[] = {
DEFINE_PROP_BOOL("cpu-little-endian", GT64120State,
cpu_little_endian, false),
DEFINE_PROP_END_OF_LIST(),

2
hw/pci-host/i440fx.c
View file

@ -353,7 +353,7 @@ static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
return "0000:00";
}
static Property i440fx_props[] = {
static const Property i440fx_props[] = {
DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT),
DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, I440FXState,

2
hw/pci-host/mv64361.c
View file

@ -98,7 +98,7 @@ static void mv64361_pcihost_realize(DeviceState *dev, Error **errp)
qdev_init_gpio_out(dev, s->irq, ARRAY_SIZE(s->irq));
}
static Property mv64361_pcihost_props[] = {
static const Property mv64361_pcihost_props[] = {
DEFINE_PROP_UINT8("index", MV64361PCIState, index, 0),
DEFINE_PROP_END_OF_LIST()
};

4
hw/pci-host/pnv_phb.c
View file

@ -183,7 +183,7 @@ static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge,
return phb->bus_path;
}
static Property pnv_phb_properties[] = {
static const Property pnv_phb_properties[] = {
DEFINE_PROP_UINT32("index", PnvPHB, phb_id, 0),
DEFINE_PROP_UINT32("chip-id", PnvPHB, chip_id, 0),
DEFINE_PROP_UINT32("version", PnvPHB, version, 0),
@ -302,7 +302,7 @@ static void pnv_phb_root_port_realize(DeviceState *dev, Error **errp)
pci_config_set_interrupt_pin(pci->config, 0);
}
static Property pnv_phb_root_port_properties[] = {
static const Property pnv_phb_root_port_properties[] = {
DEFINE_PROP_UINT32("version", PnvPHBRootPort, version, 0),
DEFINE_PROP_END_OF_LIST(),

2
hw/pci-host/pnv_phb3.c
View file

@ -1090,7 +1090,7 @@ void pnv_phb3_update_regions(PnvPHB3 *phb)
pnv_phb3_check_all_m64s(phb);
}
static Property pnv_phb3_properties[] = {
static const Property pnv_phb3_properties[] = {
DEFINE_PROP_UINT32("index", PnvPHB3, phb_id, 0),
DEFINE_PROP_UINT32("chip-id", PnvPHB3, chip_id, 0),
DEFINE_PROP_LINK("chip", PnvPHB3, chip, TYPE_PNV_CHIP, PnvChip *),

2
hw/pci-host/pnv_phb4.c
View file

@ -1688,7 +1688,7 @@ static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno,
}
}
static Property pnv_phb4_properties[] = {
static const Property pnv_phb4_properties[] = {
DEFINE_PROP_UINT32("index", PnvPHB4, phb_id, 0),
DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0),
DEFINE_PROP_LINK("pec", PnvPHB4, pec, TYPE_PNV_PHB4_PEC,

2
hw/pci-host/pnv_phb4_pec.c
View file

@ -283,7 +283,7 @@ static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt,
return 0;
}
static Property pnv_pec_properties[] = {
static const Property pnv_pec_properties[] = {
DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0),
DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0),
DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP,

2
hw/pci-host/ppce500.c
View file

@ -507,7 +507,7 @@ static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
dc->user_creatable = false;
}
static Property pcihost_properties[] = {
static const Property pcihost_properties[] = {
DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11),
DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1),
DEFINE_PROP_END_OF_LIST(),

4
hw/pci-host/q35.c
View file

@ -170,7 +170,7 @@ static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
* properties need to be initialized manually by
* q35_host_initfn() after the object_initialize() call.
*/
static Property q35_host_props[] = {
static const Property q35_host_props[] = {
DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,
MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
@ -662,7 +662,7 @@ static void mch_realize(PCIDevice *d, Error **errp)
OBJECT(&mch->smram));
}
static Property mch_props[] = {
static const Property mch_props[] = {
DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes,
16),
DEFINE_PROP_BOOL("smbase-smram", MCHPCIState, has_smram_at_smbase, true),

2
hw/pci-host/raven.c
View file

@ -422,7 +422,7 @@ static const TypeInfo raven_info = {
},
};
static Property raven_pcihost_properties[] = {
static const Property raven_pcihost_properties[] = {
DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
EM_NONE),
DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),

2
hw/pci-host/sabre.c
View file

@ -492,7 +492,7 @@ static char *sabre_ofw_unit_address(const SysBusDevice *dev)
(uint32_t)(s->special_base & 0xffffffff));
}
static Property sabre_properties[] = {
static const Property sabre_properties[] = {
DEFINE_PROP_UINT64("special-base", SabreState, special_base, 0),
DEFINE_PROP_UINT64("mem-base", SabreState, mem_base, 0),
DEFINE_PROP_END_OF_LIST(),

2
hw/pci-host/uninorth.c
View file

@ -423,7 +423,7 @@ static const TypeInfo unin_internal_pci_host_info = {
},
};
static Property pci_unin_main_pci_host_props[] = {
static const Property pci_unin_main_pci_host_props[] = {
DEFINE_PROP_UINT32("ofw-addr", UNINHostState, ofw_addr, -1),
DEFINE_PROP_END_OF_LIST()
};

2
hw/pci-host/versatile.c
View file

@ -498,7 +498,7 @@ static const TypeInfo versatile_pci_host_info = {
},
};
static Property pci_vpb_properties[] = {
static const Property pci_vpb_properties[] = {
DEFINE_PROP_UINT8("broken-irq-mapping", PCIVPBState, irq_mapping_prop,
PCI_VPB_IRQMAP_ASSUME_OK),
DEFINE_PROP_END_OF_LIST()

2
hw/pci-host/xilinx-pcie.c
View file

@ -156,7 +156,7 @@ static void xilinx_pcie_host_init(Object *obj)
qdev_prop_set_bit(DEVICE(root), "multifunction", false);
}
static Property xilinx_pcie_host_props[] = {
static const Property xilinx_pcie_host_props[] = {
DEFINE_PROP_UINT32("bus_nr", XilinxPCIEHost, bus_nr, 0),
DEFINE_PROP_SIZE("cfg_base", XilinxPCIEHost, cfg_base, 0),
DEFINE_PROP_SIZE("cfg_size", XilinxPCIEHost, cfg_size, 32 * MiB),