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target/sh4: Convert to 3-phase reset

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Convert the sh4 CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Message-id: 20221124115023.2437291-17-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-11-24 11:50:19 +00:00
parent 88c41e4082
commit 9049383002
2 changed files with 10 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

4
target/sh4/cpu-qom.h
View file

@ -34,7 +34,7 @@ OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU)
/** /**
* SuperHCPUClass: * SuperHCPUClass:
* @parent_realize: The parent class' realize handler. * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler. * @parent_phases: The parent class' reset phase handlers.
* @pvr: Processor Version Register * @pvr: Processor Version Register
* @prr: Processor Revision Register * @prr: Processor Revision Register
* @cvr: Cache Version Register * @cvr: Cache Version Register
@ -47,7 +47,7 @@ struct SuperHCPUClass {
/*< public >*/ /*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
DeviceReset parent_reset; ResettablePhases parent_phases;
uint32_t pvr; uint32_t pvr;
uint32_t prr; uint32_t prr;

12
target/sh4/cpu.c
View file

@ -87,14 +87,16 @@ static bool superh_cpu_has_work(CPUState *cs)
return cs->interrupt_request & CPU_INTERRUPT_HARD; return cs->interrupt_request & CPU_INTERRUPT_HARD;
} }
static void superh_cpu_reset(DeviceState *dev) static void superh_cpu_reset_hold(Object *obj)
{ {
CPUState *s = CPU(dev); CPUState *s = CPU(obj);
SuperHCPU *cpu = SUPERH_CPU(s); SuperHCPU *cpu = SUPERH_CPU(s);
SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu); SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
CPUSH4State *env = &cpu->env; CPUSH4State *env = &cpu->env;
scc->parent_reset(dev); if (scc->parent_phases.hold) {
scc->parent_phases.hold(obj);
}
memset(env, 0, offsetof(CPUSH4State, end_reset_fields)); memset(env, 0, offsetof(CPUSH4State, end_reset_fields));
@ -274,11 +276,13 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc); CPUClass *cc = CPU_CLASS(oc);
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, superh_cpu_realizefn, device_class_set_parent_realize(dc, superh_cpu_realizefn,
&scc->parent_realize); &scc->parent_realize);
device_class_set_parent_reset(dc, superh_cpu_reset, &scc->parent_reset); resettable_class_set_parent_phases(rc, NULL, superh_cpu_reset_hold, NULL,
&scc->parent_phases);
cc->class_by_name = superh_cpu_class_by_name; cc->class_by_name = superh_cpu_class_by_name;
cc->has_work = superh_cpu_has_work; cc->has_work = superh_cpu_has_work;