motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-11 03:24:58 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

hw/intc/loongson_ipi: Add LoongsonIPICommonClass::cpu_by_arch_id handler

Browse source 
Allow Loongson IPI implementations to have their own
cpu_by_arch_id() handler.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
[PMD: Extracted from bigger commit, added commit description]
Co-Developed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Tested-by: Bibo Mao <maobibo@loongson.cn>
Acked-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20240805180622.21001-10-philmd@linaro.org>
This commit is contained in:
Bibo Mao 2024-07-15 18:24:02 +02:00 • committed by Philippe Mathieu-Daudé
parent a81cd679d7
commit 8f4f38fd2a
2 changed files with 8 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

10
hw/intc/loongson_ipi.c
View file

@ -128,12 +128,13 @@ static MemTxResult send_ipi_data(LoongsonIPICommonState *ipi, CPUState *cpu,
static MemTxResult mail_send(LoongsonIPICommonState *ipi, static MemTxResult mail_send(LoongsonIPICommonState *ipi,
uint64_t val, MemTxAttrs attrs) uint64_t val, MemTxAttrs attrs)
{ {
LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
uint32_t cpuid; uint32_t cpuid;
hwaddr addr; hwaddr addr;
CPUState *cs; CPUState *cs;
cpuid = extract32(val, 16, 10); cpuid = extract32(val, 16, 10);
cs = cpu_by_arch_id(cpuid); cs = licc->cpu_by_arch_id(cpuid);
if (cs == NULL) { if (cs == NULL) {
return MEMTX_DECODE_ERROR; return MEMTX_DECODE_ERROR;
} }
@ -147,12 +148,13 @@ static MemTxResult mail_send(LoongsonIPICommonState *ipi,
static MemTxResult any_send(LoongsonIPICommonState *ipi, static MemTxResult any_send(LoongsonIPICommonState *ipi,
uint64_t val, MemTxAttrs attrs) uint64_t val, MemTxAttrs attrs)
{ {
LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
uint32_t cpuid; uint32_t cpuid;
hwaddr addr; hwaddr addr;
CPUState *cs; CPUState *cs;
cpuid = extract32(val, 16, 10); cpuid = extract32(val, 16, 10);
cs = cpu_by_arch_id(cpuid); cs = licc->cpu_by_arch_id(cpuid);
if (cs == NULL) { if (cs == NULL) {
return MEMTX_DECODE_ERROR; return MEMTX_DECODE_ERROR;
} }
@ -169,6 +171,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr,
{ {
IPICore *s = opaque; IPICore *s = opaque;
LoongsonIPICommonState *ipi = s->ipi; LoongsonIPICommonState *ipi = s->ipi;
LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_GET_CLASS(ipi);
int index = 0; int index = 0;
uint32_t cpuid; uint32_t cpuid;
uint8_t vector; uint8_t vector;
@ -203,7 +206,7 @@ static MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr,
cpuid = extract32(val, 16, 10); cpuid = extract32(val, 16, 10);
/* IPI status vector */ /* IPI status vector */
vector = extract8(val, 0, 5); vector = extract8(val, 0, 5);
cs = cpu_by_arch_id(cpuid); cs = licc->cpu_by_arch_id(cpuid);
if (cs == NULL || cs->cpu_index >= ipi->num_cpu) { if (cs == NULL || cs->cpu_index >= ipi->num_cpu) {
return MEMTX_DECODE_ERROR; return MEMTX_DECODE_ERROR;
} }
@ -367,6 +370,7 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data)
device_class_set_parent_unrealize(dc, loongson_ipi_unrealize, device_class_set_parent_unrealize(dc, loongson_ipi_unrealize,
&lic->parent_unrealize); &lic->parent_unrealize);
licc->get_iocsr_as = get_iocsr_as; licc->get_iocsr_as = get_iocsr_as;
licc->cpu_by_arch_id = cpu_by_arch_id;
} }
static const TypeInfo loongson_ipi_types[] = { static const TypeInfo loongson_ipi_types[] = {

1
include/hw/intc/loongson_ipi_common.h
View file

@ -41,6 +41,7 @@ struct LoongsonIPICommonClass {
SysBusDeviceClass parent_class; SysBusDeviceClass parent_class;
AddressSpace *(*get_iocsr_as)(CPUState *cpu); AddressSpace *(*get_iocsr_as)(CPUState *cpu);
CPUState *(*cpu_by_arch_id)(int64_t id);
}; };
/* Mainy used by iocsr read and write */ /* Mainy used by iocsr read and write */