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target/arm: Make gen_swap_half() take separate src and dest

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Make gen_swap_half() take a source and destination TCGv_i32 rather
than modifying the input TCGv_i32; we're going to want to be able to
use it with the more flexible function signature, and this also
brings it into line with other functions like gen_rev16() and
gen_revsh().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-12-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-06-16 18:08:34 +01:00
parent 5de3fd045b
commit 8ec3de7018
2 changed files with 6 additions and 6 deletions
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2
target/arm/translate-neon.inc.c
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@ -3007,7 +3007,7 @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
tcg_gen_bswap32_i32(tmp[half], tmp[half]); tcg_gen_bswap32_i32(tmp[half], tmp[half]);
break; break;
case 1: case 1:
gen_swap_half(tmp[half]); gen_swap_half(tmp[half], tmp[half]);
break; break;
case 2: case 2:
break; break;

10
target/arm/translate.c
View file

@ -378,9 +378,9 @@ static void gen_revsh(TCGv_i32 dest, TCGv_i32 var)
} }
/* Swap low and high halfwords. */ /* Swap low and high halfwords. */
static void gen_swap_half(TCGv_i32 var) static void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
{ {
tcg_gen_rotri_i32(var, var, 16); tcg_gen_rotri_i32(dest, var, 16);
} }
/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead. /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
@ -4960,7 +4960,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
case NEON_2RM_VREV32: case NEON_2RM_VREV32:
switch (size) { switch (size) {
case 0: tcg_gen_bswap32_i32(tmp, tmp); break; case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
case 1: gen_swap_half(tmp); break; case 1: gen_swap_half(tmp, tmp); break;
default: abort(); default: abort();
} }
break; break;
@ -8046,7 +8046,7 @@ static bool op_smlad(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub)
t1 = load_reg(s, a->rn); t1 = load_reg(s, a->rn);
t2 = load_reg(s, a->rm); t2 = load_reg(s, a->rm);
if (m_swap) { if (m_swap) {
gen_swap_half(t2); gen_swap_half(t2, t2);
} }
gen_smul_dual(t1, t2); gen_smul_dual(t1, t2);
@ -8104,7 +8104,7 @@ static bool op_smlald(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub)
t1 = load_reg(s, a->rn); t1 = load_reg(s, a->rn);
t2 = load_reg(s, a->rm); t2 = load_reg(s, a->rm);
if (m_swap) { if (m_swap) {
gen_swap_half(t2); gen_swap_half(t2, t2);
} }
gen_smul_dual(t1, t2); gen_smul_dual(t1, t2);