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target/arm: Convert Neon VRHADD, VHSUB 3-reg-same insns to decodetree

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Convert the Neon VRHADD and VHSUB 3-reg-same insns to decodetree.
(These are all the other insns in 3-reg-same which were using
GEN_NEON_INTEGER_OP() and which are not pairwise or
reversed-operands.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200512163904.10918-7-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-05-12 17:38:53 +01:00
parent 7715098f93
commit 8e44d03f4b
3 changed files with 12 additions and 6 deletions
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8
target/arm/translate.c
View file

@ -5435,6 +5435,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
case NEON_3R_VSHL:
case NEON_3R_SHA:
case NEON_3R_VHADD:
case NEON_3R_VRHADD:
case NEON_3R_VHSUB:
case NEON_3R_VABD:
case NEON_3R_VABA:
/* Already handled by decodetree */
@ -5517,12 +5519,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
tmp2 = neon_load_reg(rm, pass);
}
switch (op) {
case NEON_3R_VRHADD:
GEN_NEON_INTEGER_OP(rhadd);
break;
case NEON_3R_VHSUB:
GEN_NEON_INTEGER_OP(hsub);
break;
case NEON_3R_VQSHL:
GEN_NEON_INTEGER_OP_ENV(qshl);
break;