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usb/hcd-xhci: Split pci wrapper for xhci base model
This patch sets the base to use xhci as sysbus model, for which pci specific hooks are moved to hcd-xhci-pci.c. As a part of this requirment msi/msix interrupts handling is moved under XHCIPCIState. Made required changes for qemu-xhci-nec. Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Message-id: 1600957256-6494-4-git-send-email-sai.pavan.boddu@xilinx.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
This commit is contained in:
Sai Pavan Boddu
Gerd Hoffmann
parent
755fba11fb
commit
8ddab8dd3d
5 changed files with 303 additions and 193 deletions
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@ -24,10 +24,7 @@
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#include "qemu/module.h"
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#include "qemu/queue.h"
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#include "migration/vmstate.h"
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#include "hw/pci/pci.h"
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#include "hw/qdev-properties.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/msix.h"
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#include "trace.h"
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#include "qapi/error.h"
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@ -56,8 +53,6 @@
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#define OFF_OPER LEN_CAP
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#define OFF_RUNTIME 0x1000
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#define OFF_DOORBELL 0x2000
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#define OFF_MSIX_TABLE 0x3000
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#define OFF_MSIX_PBA 0x3800
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/* must be power of 2 */
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#define LEN_REGS 0x4000
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@ -547,54 +542,28 @@ static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
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return &xhci->ports[index];
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}
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static void xhci_intx_update(XHCIState *xhci)
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static void xhci_intr_update(XHCIState *xhci, int v)
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{
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PCIDevice *pci_dev = PCI_DEVICE(xhci);
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int level = 0;
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if (msix_enabled(pci_dev) ||
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msi_enabled(pci_dev)) {
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return;
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if (v == 0) {
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if (xhci->intr[0].iman & IMAN_IP &&
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xhci->intr[0].iman & IMAN_IE &&
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xhci->usbcmd & USBCMD_INTE) {
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level = 1;
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}
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if (xhci->intr_raise) {
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xhci->intr_raise(xhci, 0, level);
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}
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}
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if (xhci->intr[0].iman & IMAN_IP &&
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xhci->intr[0].iman & IMAN_IE &&
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xhci->usbcmd & USBCMD_INTE) {
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level = 1;
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}
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trace_usb_xhci_irq_intx(level);
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pci_set_irq(pci_dev, level);
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}
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static void xhci_msix_update(XHCIState *xhci, int v)
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{
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PCIDevice *pci_dev = PCI_DEVICE(xhci);
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bool enabled;
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if (!msix_enabled(pci_dev)) {
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return;
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}
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enabled = xhci->intr[v].iman & IMAN_IE;
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if (enabled == xhci->intr[v].msix_used) {
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return;
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}
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if (enabled) {
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trace_usb_xhci_irq_msix_use(v);
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msix_vector_use(pci_dev, v);
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xhci->intr[v].msix_used = true;
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} else {
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trace_usb_xhci_irq_msix_unuse(v);
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msix_vector_unuse(pci_dev, v);
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xhci->intr[v].msix_used = false;
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if (xhci->intr_update) {
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xhci->intr_update(xhci, v,
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xhci->intr[v].iman & IMAN_IE);
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}
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}
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static void xhci_intr_raise(XHCIState *xhci, int v)
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{
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PCIDevice *pci_dev = PCI_DEVICE(xhci);
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bool pending = (xhci->intr[v].erdp_low & ERDP_EHB);
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xhci->intr[v].erdp_low |= ERDP_EHB;
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@ -611,22 +580,8 @@ static void xhci_intr_raise(XHCIState *xhci, int v)
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if (!(xhci->usbcmd & USBCMD_INTE)) {
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return;
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}
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if (msix_enabled(pci_dev)) {
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trace_usb_xhci_irq_msix(v);
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msix_notify(pci_dev, v);
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return;
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}
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if (msi_enabled(pci_dev)) {
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trace_usb_xhci_irq_msi(v);
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msi_notify(pci_dev, v);
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return;
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}
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if (v == 0) {
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trace_usb_xhci_irq_intx(1);
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pci_irq_assert(pci_dev);
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if (xhci->intr_raise) {
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xhci->intr_raise(xhci, v, true);
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}
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}
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@ -2717,7 +2672,6 @@ static void xhci_reset(DeviceState *dev)
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xhci->intr[i].erstba_high = 0;
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xhci->intr[i].erdp_low = 0;
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xhci->intr[i].erdp_high = 0;
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xhci->intr[i].msix_used = 0;
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xhci->intr[i].er_ep_idx = 0;
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xhci->intr[i].er_pcs = 1;
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@ -2939,8 +2893,7 @@ static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
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static void xhci_oper_write(void *ptr, hwaddr reg,
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uint64_t val, unsigned size)
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{
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XHCIState *xhci = ptr;
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DeviceState *d = DEVICE(ptr);
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XHCIState *xhci = XHCI(ptr);
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trace_usb_xhci_oper_write(reg, val);
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@ -2962,15 +2915,15 @@ static void xhci_oper_write(void *ptr, hwaddr reg,
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xhci->usbcmd = val & 0xc0f;
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xhci_mfwrap_update(xhci);
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if (val & USBCMD_HCRST) {
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xhci_reset(d);
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xhci_reset(DEVICE(xhci));
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}
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xhci_intx_update(xhci);
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xhci_intr_update(xhci, 0);
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break;
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case 0x04: /* USBSTS */
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/* these bits are write-1-to-clear */
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xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
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xhci_intx_update(xhci);
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xhci_intr_update(xhci, 0);
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break;
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case 0x14: /* DNCTRL */
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@ -3073,10 +3026,7 @@ static void xhci_runtime_write(void *ptr, hwaddr reg,
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}
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intr->iman &= ~IMAN_IE;
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intr->iman |= val & IMAN_IE;
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if (v == 0) {
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xhci_intx_update(xhci);
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}
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xhci_msix_update(xhci, v);
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xhci_intr_update(xhci, v);
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break;
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case 0x04: /* IMOD */
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intr->imod = val;
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@ -3321,7 +3271,6 @@ static USBBusOps xhci_bus_ops = {
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static void usb_xhci_init(XHCIState *xhci)
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{
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DeviceState *dev = DEVICE(xhci);
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XHCIPort *port;
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unsigned int i, usbports, speedmask;
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@ -3336,7 +3285,7 @@ static void usb_xhci_init(XHCIState *xhci)
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usbports = MAX(xhci->numports_2, xhci->numports_3);
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xhci->numports = xhci->numports_2 + xhci->numports_3;
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usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev);
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usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, xhci->hostOpaque);
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for (i = 0; i < usbports; i++) {
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speedmask = 0;
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@ -3376,21 +3325,12 @@ static void usb_xhci_init(XHCIState *xhci)
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}
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}
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static void usb_xhci_realize(struct PCIDevice *dev, Error **errp)
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static void usb_xhci_realize(DeviceState *dev, Error **errp)
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{
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int i, ret;
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Error *err = NULL;
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int i;
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XHCIState *xhci = XHCI(dev);
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dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */
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dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
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dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
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dev->config[0x60] = 0x30; /* release number */
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if (strcmp(object_get_typename(OBJECT(dev)), TYPE_NEC_XHCI) == 0) {
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xhci->nec_quirks = true;
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}
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if (xhci->numintrs > MAXINTRS) {
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xhci->numintrs = MAXINTRS;
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}
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@ -3412,36 +3352,18 @@ static void usb_xhci_realize(struct PCIDevice *dev, Error **errp)
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xhci->max_pstreams_mask = 0;
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}
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if (xhci->msi != ON_OFF_AUTO_OFF) {
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ret = msi_init(dev, 0x70, xhci->numintrs, true, false, &err);
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/* Any error other than -ENOTSUP(board's MSI support is broken)
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* is a programming error */
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assert(!ret || ret == -ENOTSUP);
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if (ret && xhci->msi == ON_OFF_AUTO_ON) {
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/* Can't satisfy user's explicit msi=on request, fail */
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error_append_hint(&err, "You have to use msi=auto (default) or "
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"msi=off with this machine type.\n");
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error_propagate(errp, err);
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return;
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}
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assert(!err || xhci->msi == ON_OFF_AUTO_AUTO);
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/* With msi=auto, we fall back to MSI off silently */
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error_free(err);
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}
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usb_xhci_init(xhci);
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xhci->as = pci_get_address_space(dev);
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xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
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memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS);
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memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci,
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memory_region_init(&xhci->mem, OBJECT(dev), "xhci", LEN_REGS);
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memory_region_init_io(&xhci->mem_cap, OBJECT(dev), &xhci_cap_ops, xhci,
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"capabilities", LEN_CAP);
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memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci,
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memory_region_init_io(&xhci->mem_oper, OBJECT(dev), &xhci_oper_ops, xhci,
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"operational", 0x400);
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memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci,
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"runtime", LEN_RUNTIME);
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memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci,
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"doorbell", LEN_DOORBELL);
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memory_region_init_io(&xhci->mem_runtime, OBJECT(dev), &xhci_runtime_ops,
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xhci, "runtime", LEN_RUNTIME);
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memory_region_init_io(&xhci->mem_doorbell, OBJECT(dev), &xhci_doorbell_ops,
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xhci, "doorbell", LEN_DOORBELL);
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memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
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memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper);
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@ -3452,31 +3374,13 @@ static void usb_xhci_realize(struct PCIDevice *dev, Error **errp)
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XHCIPort *port = &xhci->ports[i];
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uint32_t offset = OFF_OPER + 0x400 + 0x10 * i;
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port->xhci = xhci;
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memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port,
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memory_region_init_io(&port->mem, OBJECT(dev), &xhci_port_ops, port,
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port->name, 0x10);
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memory_region_add_subregion(&xhci->mem, offset, &port->mem);
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}
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pci_register_bar(dev, 0,
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PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
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&xhci->mem);
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if (pci_bus_is_express(pci_get_bus(dev)) ||
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xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) {
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ret = pcie_endpoint_cap_init(dev, 0xa0);
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assert(ret > 0);
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}
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if (xhci->msix != ON_OFF_AUTO_OFF) {
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/* TODO check for errors, and should fail when msix=on */
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msix_init(dev, xhci->numintrs,
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&xhci->mem, 0, OFF_MSIX_TABLE,
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&xhci->mem, 0, OFF_MSIX_PBA,
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0x90, NULL);
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}
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}
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static void usb_xhci_exit(PCIDevice *dev)
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static void usb_xhci_unrealize(DeviceState *dev)
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{
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int i;
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XHCIState *xhci = XHCI(dev);
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@ -3503,25 +3407,18 @@ static void usb_xhci_exit(PCIDevice *dev)
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memory_region_del_subregion(&xhci->mem, &port->mem);
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}
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/* destroy msix memory region */
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if (dev->msix_table && dev->msix_pba
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&& dev->msix_entry_used) {
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msix_uninit(dev, &xhci->mem, &xhci->mem);
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}
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usb_bus_release(&xhci->bus);
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}
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static int usb_xhci_post_load(void *opaque, int version_id)
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{
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XHCIState *xhci = opaque;
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PCIDevice *pci_dev = PCI_DEVICE(xhci);
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XHCISlot *slot;
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XHCIEPContext *epctx;
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dma_addr_t dcbaap, pctx;
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uint32_t slot_ctx[4];
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uint32_t ep_ctx[5];
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int slotid, epid, state, intr;
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int slotid, epid, state;
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dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
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@ -3559,15 +3456,6 @@ static int usb_xhci_post_load(void *opaque, int version_id)
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}
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}
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}
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for (intr = 0; intr < xhci->numintrs; intr++) {
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if (xhci->intr[intr].msix_used) {
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msix_vector_use(pci_dev, intr);
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} else {
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msix_vector_unuse(pci_dev, intr);
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}
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}
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return 0;
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}
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@ -3652,14 +3540,11 @@ static const VMStateDescription vmstate_xhci_intr = {
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}
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};
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static const VMStateDescription vmstate_xhci = {
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.name = "xhci",
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const VMStateDescription vmstate_xhci = {
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.name = "xhci-core",
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.version_id = 1,
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.post_load = usb_xhci_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(parent_obj, XHCIState),
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VMSTATE_MSIX(parent_obj, XHCIState),
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VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,
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vmstate_xhci_port, XHCIPort),
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VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1,
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@ -3691,42 +3576,27 @@ static Property xhci_properties[] = {
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XHCI_FLAG_ENABLE_STREAMS, true),
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DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4),
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DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4),
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DEFINE_PROP_LINK("host", XHCIState, hostOpaque, TYPE_DEVICE,
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DeviceState *),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void xhci_instance_init(Object *obj)
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{
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/* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command
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* line, therefore, no need to wait to realize like other devices */
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PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS;
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}
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static void xhci_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &vmstate_xhci;
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device_class_set_props(dc, xhci_properties);
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dc->realize = usb_xhci_realize;
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dc->unrealize = usb_xhci_unrealize;
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dc->reset = xhci_reset;
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set_bit(DEVICE_CATEGORY_USB, dc->categories);
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k->realize = usb_xhci_realize;
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k->exit = usb_xhci_exit;
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k->class_id = PCI_CLASS_SERIAL_USB;
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device_class_set_props(dc, xhci_properties);
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dc->user_creatable = false;
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}
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static const TypeInfo xhci_info = {
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.name = TYPE_XHCI,
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.parent = TYPE_PCI_DEVICE,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(XHCIState),
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.class_init = xhci_class_init,
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.instance_init = xhci_instance_init,
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.abstract = true,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_PCIE_DEVICE },
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ }
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},
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};
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static void xhci_register_types(void)
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Add a link
Reference in a new issue