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https://github.com/Motorhead1991/qemu.git
synced 2025-08-05 00:33:55 -06:00
Change MMIO callbacks to use offsets, not absolute addresses.
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5849 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
pbrook
parent
6ad1d22b15
commit
8da3ff1809
82 changed files with 453 additions and 869 deletions
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@ -106,7 +106,6 @@ struct omap_dma_s {
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struct soc_dma_s *dma;
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struct omap_mpu_state_s *mpu;
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target_phys_addr_t base;
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omap_clk clk;
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qemu_irq irq[4];
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void (*intr_update)(struct omap_dma_s *s);
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@ -1447,20 +1446,20 @@ static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
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static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
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{
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struct omap_dma_s *s = (struct omap_dma_s *) opaque;
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int reg, ch, offset = addr - s->base;
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int reg, ch;
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uint16_t ret;
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switch (offset) {
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switch (addr) {
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case 0x300 ... 0x3fe:
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if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
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if (omap_dma_3_1_lcd_read(&s->lcd_ch, offset, &ret))
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if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret))
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break;
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return ret;
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}
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/* Fall through. */
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case 0x000 ... 0x2fe:
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reg = offset & 0x3f;
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ch = (offset >> 6) & 0x0f;
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reg = addr & 0x3f;
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ch = (addr >> 6) & 0x0f;
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if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
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break;
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return ret;
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@ -1470,13 +1469,13 @@ static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
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break;
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/* Fall through. */
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case 0x400:
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if (omap_dma_sys_read(s, offset, &ret))
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if (omap_dma_sys_read(s, addr, &ret))
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break;
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return ret;
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case 0xb00 ... 0xbfe:
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if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
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if (omap_dma_3_2_lcd_read(&s->lcd_ch, offset, &ret))
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if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret))
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break;
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return ret;
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}
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@ -1491,19 +1490,19 @@ static void omap_dma_write(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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struct omap_dma_s *s = (struct omap_dma_s *) opaque;
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int reg, ch, offset = addr - s->base;
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int reg, ch;
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switch (offset) {
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switch (addr) {
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case 0x300 ... 0x3fe:
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if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
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if (omap_dma_3_1_lcd_write(&s->lcd_ch, offset, value))
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if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value))
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break;
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return;
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}
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/* Fall through. */
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case 0x000 ... 0x2fe:
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reg = offset & 0x3f;
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ch = (offset >> 6) & 0x0f;
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reg = addr & 0x3f;
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ch = (addr >> 6) & 0x0f;
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if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
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break;
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return;
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@ -1513,13 +1512,13 @@ static void omap_dma_write(void *opaque, target_phys_addr_t addr,
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break;
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case 0x400:
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/* Fall through. */
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if (omap_dma_sys_write(s, offset, value))
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if (omap_dma_sys_write(s, addr, value))
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break;
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return;
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case 0xb00 ... 0xbfe:
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if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
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if (omap_dma_3_2_lcd_write(&s->lcd_ch, offset, value))
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if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value))
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break;
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return;
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}
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@ -1628,7 +1627,6 @@ struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
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num_irqs = 16;
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memsize = 0xc00;
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}
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s->base = base;
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s->model = model;
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s->mpu = mpu;
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s->clk = clk;
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@ -1660,7 +1658,7 @@ struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
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iomemtype = cpu_register_io_memory(0, omap_dma_readfn,
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omap_dma_writefn, s);
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cpu_register_physical_memory(s->base, memsize, iomemtype);
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cpu_register_physical_memory(base, memsize, iomemtype);
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mpu->drq = s->dma->drq;
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@ -1691,10 +1689,10 @@ static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
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static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr)
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{
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struct omap_dma_s *s = (struct omap_dma_s *) opaque;
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int irqn = 0, chnum, offset = addr - s->base;
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int irqn = 0, chnum;
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struct omap_dma_channel_s *ch;
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switch (offset) {
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switch (addr) {
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case 0x00: /* DMA4_REVISION */
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return 0x40;
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@ -1735,10 +1733,10 @@ static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr)
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return s->gcr;
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case 0x80 ... 0xfff:
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offset -= 0x80;
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chnum = offset / 0x60;
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addr -= 0x80;
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chnum = addr / 0x60;
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ch = s->ch + chnum;
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offset -= chnum * 0x60;
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addr -= chnum * 0x60;
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break;
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default:
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@ -1747,7 +1745,7 @@ static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr)
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}
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/* Per-channel registers */
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switch (offset) {
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switch (addr) {
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case 0x00: /* DMA4_CCR */
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return (ch->buf_disable << 25) |
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(ch->src_sync << 24) |
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@ -1837,10 +1835,10 @@ static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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struct omap_dma_s *s = (struct omap_dma_s *) opaque;
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int chnum, irqn = 0, offset = addr - s->base;
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int chnum, irqn = 0;
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struct omap_dma_channel_s *ch;
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switch (offset) {
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switch (addr) {
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case 0x14: /* DMA4_IRQSTATUS_L3 */
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irqn ++;
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case 0x10: /* DMA4_IRQSTATUS_L2 */
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@ -1878,10 +1876,10 @@ static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
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return;
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case 0x80 ... 0xfff:
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offset -= 0x80;
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chnum = offset / 0x60;
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addr -= 0x80;
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chnum = addr / 0x60;
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ch = s->ch + chnum;
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offset -= chnum * 0x60;
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addr -= chnum * 0x60;
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break;
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case 0x00: /* DMA4_REVISION */
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@ -1899,7 +1897,7 @@ static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
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}
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/* Per-channel registers */
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switch (offset) {
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switch (addr) {
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case 0x00: /* DMA4_CCR */
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ch->buf_disable = (value >> 25) & 1;
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ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */
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@ -2041,7 +2039,6 @@ struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
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struct omap_dma_s *s = (struct omap_dma_s *)
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qemu_mallocz(sizeof(struct omap_dma_s));
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s->base = base;
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s->model = omap_dma_4;
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s->chans = chans;
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s->mpu = mpu;
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@ -2068,7 +2065,7 @@ struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
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iomemtype = cpu_register_io_memory(0, omap_dma4_readfn,
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omap_dma4_writefn, s);
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cpu_register_physical_memory(s->base, 0x1000, iomemtype);
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cpu_register_physical_memory(base, 0x1000, iomemtype);
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mpu->drq = s->dma->drq;
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