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Change MMIO callbacks to use offsets, not absolute addresses.

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Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5849 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
pbrook 2008-12-01 18:59:50 +00:00
parent 6ad1d22b15
commit 8da3ff1809
82 changed files with 453 additions and 869 deletions
Download patch file Download diff file Expand all files Collapse all files

8
hw/arm_timer.c
View file

@ -190,7 +190,6 @@ static void *arm_timer_init(uint32_t freq, qemu_irq irq)
typedef struct {
void *timer[2];
int level[2];
uint32_t base;
qemu_irq irq;
} sp804_state;
@ -208,7 +207,6 @@ static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
sp804_state *s = (sp804_state *)opaque;
/* ??? Don't know the PrimeCell ID for this device. */
offset -= s->base;
if (offset < 0x20) {
return arm_timer_read(s->timer[0], offset);
} else {
@ -221,7 +219,6 @@ static void sp804_write(void *opaque, target_phys_addr_t offset,
{
sp804_state *s = (sp804_state *)opaque;
offset -= s->base;
if (offset < 0x20) {
arm_timer_write(s->timer[0], offset, value);
} else {
@ -268,7 +265,6 @@ void sp804_init(uint32_t base, qemu_irq irq)
s = (sp804_state *)qemu_mallocz(sizeof(sp804_state));
qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
s->base = base;
s->irq = irq;
/* ??? The timers are actually configurable between 32kHz and 1MHz, but
we don't implement that. */
@ -285,7 +281,6 @@ void sp804_init(uint32_t base, qemu_irq irq)
typedef struct {
void *timer[3];
uint32_t base;
} icp_pit_state;
static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
@ -294,7 +289,6 @@ static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
int n;
/* ??? Don't know the PrimeCell ID for this device. */
offset -= s->base;
n = offset >> 8;
if (n > 3)
cpu_abort(cpu_single_env, "sp804_read: Bad timer %d\n", n);
@ -308,7 +302,6 @@ static void icp_pit_write(void *opaque, target_phys_addr_t offset,
icp_pit_state *s = (icp_pit_state *)opaque;
int n;
offset -= s->base;
n = offset >> 8;
if (n > 3)
cpu_abort(cpu_single_env, "sp804_write: Bad timer %d\n", n);
@ -335,7 +328,6 @@ void icp_pit_init(uint32_t base, qemu_irq *pic, int irq)
icp_pit_state *s;
s = (icp_pit_state *)qemu_mallocz(sizeof(icp_pit_state));
s->base = base;
/* Timer 0 runs at the system clock speed (40MHz). */
s->timer[0] = arm_timer_init(40000000, pic[irq]);
/* The other two timers run at 1MHz. */